fsk.flow.rpt

通信系统的FSK调制程序

Flow report for FSK
Thu Jun 12 10:23:35 2008
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Flow Summary                                                                       ;
+------------------------------------+-----------------------------------------------+
; Flow Status                        ; Successful - Thu Jun 12 10:23:35 2008         ;
; Quartus II Version                 ; 7.2 Build 175 11/20/2007 SP 1 SJ Full Version ;
; Revision Name                      ; FSK                                           ;
; Top-level Entity Name              ; FSK                                           ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C5Q208C8                                   ;
; Timing Models                      ; Final                                         ;
; Met timing requirements            ; No                                            ;
; Total logic elements               ; 39 / 4,608 ( < 1 % )                          ;
;     Total combinational functions  ; 39 / 4,608 ( < 1 % )                          ;
;     Dedicated logic registers      ; 27 / 4,608 ( < 1 % )                          ;
; Total registers                    ; 27                                            ;
; Total pins                         ; 5 / 142 ( 4 % )                               ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0 / 119,808 ( 0 % )                           ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % )                                ;
; Total PLLs                         ; 0 / 2 ( 0 % )                                 ;
+------------------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 06/12/2008 10:23:21 ;
; Main task         ; Compilation         ;
; Revision Name     ; FSK                 ;
+-------------------+---------------------+


+-----------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                    ;
+------------------------------------+-----------------+---------------+-------------+----------------+
; Assignment Name                    ; Value           ; Default Value ; Entity Name ; Section Id     ;
+------------------------------------+-----------------+---------------+-------------+----------------+
; CYCLONEII_OPTIMIZATION_TECHNIQUE   ; Area            ; Balanced      ; --          ; --             ;
; EDA_OUTPUT_DATA_FORMAT             ; Vhdl            ; --            ; --          ; eda_simulation ;
; EDA_SIMULATION_TOOL                ; ModelSim (VHDL) ; <None>        ; --          ; --             ;
; PARTITION_COLOR                    ; 2147039         ; --            ; --          ; Top            ;
; PARTITION_NETLIST_TYPE             ; SOURCE          ; --            ; --          ; Top            ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off             ; --            ; --          ; eda_palace     ;
+------------------------------------+-----------------+---------------+-------------+----------------+


+------------------------------------------------------------------+
; Flow Elapsed Time                                                ;
+-------------------------+--------------+-------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ;
; Fitter                  ; 00:00:04     ; 1.0                     ;
; Assembler               ; 00:00:03     ; 1.0                     ;
; Classic Timing Analyzer ; 00:00:00     ; 1.0                     ;
; EDA Netlist Writer      ; 00:00:00     ; 1.0                     ;
; Total                   ; 00:00:09     ; --                      ;
+-------------------------+--------------+-------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off FSK -c FSK
quartus_fit --read_settings_files=off --write_settings_files=off FSK -c FSK
quartus_asm --read_settings_files=off --write_settings_files=off FSK -c FSK
quartus_tan --read_settings_files=off --write_settings_files=off FSK -c FSK --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off FSK -c FSK