fsk.vho

通信系统的FSK调制程序

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version"

-- DATE "06/12/2008 10:23:35"

-- 
-- Device: Altera EP2C5Q208C8 Package PQFP208
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	FSK IS
    PORT (
	FSK_out : OUT std_logic;
	clk : IN std_logic;
	Base_Sin : IN std_logic;
	Demod : OUT std_logic;
	led : OUT std_logic
	);
END FSK;

ARCHITECTURE structure OF FSK IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_FSK_out : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_Base_Sin : std_logic;
SIGNAL ww_Demod : std_logic;
SIGNAL ww_led : std_logic;
SIGNAL \inst1|FSK_out~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst|cnt[8]~150_combout\ : std_logic;
SIGNAL \inst|cnt[15]~164_combout\ : std_logic;
SIGNAL \inst|cnt[17]~168_combout\ : std_logic;
SIGNAL \inst|cnt[18]~170_combout\ : std_logic;
SIGNAL \inst|cnt[20]~174_combout\ : std_logic;
SIGNAL \inst2|cnt[4]~92_combout\ : std_logic;
SIGNAL \inst2|LessThan0~108_combout\ : std_logic;
SIGNAL \inst1|FSK_out~clkctrl_outclk\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \inst2|cnt[1]~86_combout\ : std_logic;
SIGNAL \inst2|cnt[1]~87\ : std_logic;
SIGNAL \inst2|cnt[2]~88_combout\ : std_logic;
SIGNAL \inst2|cnt[2]~89\ : std_logic;
SIGNAL \inst2|cnt[3]~90_combout\ : std_logic;
SIGNAL \Base_Sin~combout\ : std_logic;
SIGNAL \inst1|FSK_out~10_combout\ : std_logic;
SIGNAL \inst1|FSK_out~regout\ : std_logic;
SIGNAL \inst2|cnt[3]~91\ : std_logic;
SIGNAL \inst2|cnt[4]~93\ : std_logic;
SIGNAL \inst2|cnt[5]~94_combout\ : std_logic;
SIGNAL \inst2|cnt[5]~95\ : std_logic;
SIGNAL \inst2|cnt[6]~96_combout\ : std_logic;
SIGNAL \inst2|cnt[6]~97\ : std_logic;
SIGNAL \inst2|cnt[7]~98_combout\ : std_logic;
SIGNAL \inst2|cnt[0]~100_combout\ : std_logic;
SIGNAL \inst2|LessThan0~107_combout\ : std_logic;
SIGNAL \inst2|LessThan0~109_combout\ : std_logic;
SIGNAL \inst2|m[0]~206_combout\ : std_logic;
SIGNAL \inst2|m[1]~205_combout\ : std_logic;
SIGNAL \inst2|m[2]~204_combout\ : std_logic;
SIGNAL \inst2|LessThan1~24_combout\ : std_logic;
SIGNAL \inst2|Demod~combout\ : std_logic;
SIGNAL \clk~clkctrl_outclk\ : std_logic;
SIGNAL \inst|cnt[8]~137_cout\ : std_logic;
SIGNAL \inst|cnt[8]~139_cout\ : std_logic;
SIGNAL \inst|cnt[8]~141_cout\ : std_logic;
SIGNAL \inst|cnt[8]~143_cout\ : std_logic;
SIGNAL \inst|cnt[8]~145_cout\ : std_logic;
SIGNAL \inst|cnt[8]~147_cout\ : std_logic;
SIGNAL \inst|cnt[8]~149_cout\ : std_logic;
SIGNAL \inst|cnt[8]~151\ : std_logic;
SIGNAL \inst|cnt[9]~152_combout\ : std_logic;
SIGNAL \inst|cnt[9]~153\ : std_logic;
SIGNAL \inst|cnt[10]~154_combout\ : std_logic;
SIGNAL \inst|cnt[10]~155\ : std_logic;
SIGNAL \inst|cnt[11]~156_combout\ : std_logic;
SIGNAL \inst|cnt[11]~157\ : std_logic;
SIGNAL \inst|cnt[12]~158_combout\ : std_logic;
SIGNAL \inst|cnt[12]~159\ : std_logic;
SIGNAL \inst|cnt[13]~160_combout\ : std_logic;
SIGNAL \inst|cnt[13]~161\ : std_logic;
SIGNAL \inst|cnt[14]~162_combout\ : std_logic;
SIGNAL \inst|cnt[14]~163\ : std_logic;
SIGNAL \inst|cnt[15]~165\ : std_logic;
SIGNAL \inst|cnt[16]~166_combout\ : std_logic;
SIGNAL \inst|cnt[16]~167\ : std_logic;
SIGNAL \inst|cnt[17]~169\ : std_logic;
SIGNAL \inst|cnt[18]~171\ : std_logic;
SIGNAL \inst|cnt[19]~172_combout\ : std_logic;
SIGNAL \inst|cnt[19]~173\ : std_logic;
SIGNAL \inst|cnt[20]~175\ : std_logic;
SIGNAL \inst|cnt[21]~176_combout\ : std_logic;
SIGNAL \inst|cnt[21]~177\ : std_logic;
SIGNAL \inst|cnt[22]~178_combout\ : std_logic;
SIGNAL \inst2|cnt\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst2|m\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \inst|cnt\ : std_logic_vector(24 DOWNTO 0);

BEGIN

FSK_out <= ww_FSK_out;
ww_clk <= clk;
ww_Base_Sin <= Base_Sin;
Demod <= ww_Demod;
led <= ww_led;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\inst1|FSK_out~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \inst1|FSK_out~regout\);

\clk~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\);

\inst2|cnt[4]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~combout\,
	datain => \inst2|cnt[4]~92_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst2|cnt\(4));

\inst|cnt[20]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \inst|cnt[20]~174_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|cnt\(20));

\inst|cnt[18]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \inst|cnt[18]~170_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|cnt\(18));

\inst|cnt[17]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \inst|cnt[17]~168_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|cnt\(17));

\inst|cnt[15]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \inst|cnt[15]~164_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|cnt\(15));

\inst|cnt[8]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \inst|cnt[8]~150_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|cnt\(8));

\inst|cnt[8]~150\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|cnt[8]~150_combout\ = \inst|cnt\(8) & !\inst|cnt[8]~149_cout\ # !\inst|cnt\(8) & (\inst|cnt[8]~149_cout\ # GND)
-- \inst|cnt[8]~151\ = CARRY(!\inst|cnt[8]~149_cout\ # !\inst|cnt\(8))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|cnt\(8),
	datad => VCC,
	cin => \inst|cnt[8]~149_cout\,
	combout => \inst|cnt[8]~150_combout\,
	cout => \inst|cnt[8]~151\);

\inst|cnt[15]~164\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|cnt[15]~164_combout\ = \inst|cnt\(15) & (\inst|cnt[14]~163\ $ GND) # !\inst|cnt\(15) & !\inst|cnt[14]~163\ & VCC
-- \inst|cnt[15]~165\ = CARRY(\inst|cnt\(15) & !\inst|cnt[14]~163\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|cnt\(15),
	datad => VCC,
	cin => \inst|cnt[14]~163\,
	combout => \inst|cnt[15]~164_combout\,
	cout => \inst|cnt[15]~165\);

\inst|cnt[17]~168\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|cnt[17]~168_combout\ = \inst|cnt\(17) & (\inst|cnt[16]~167\ $ GND) # !\inst|cnt\(17) & !\inst|cnt[16]~167\ & VCC
-- \inst|cnt[17]~169\ = CARRY(\inst|cnt\(17) & !\inst|cnt[16]~167\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|cnt\(17),
	datad => VCC,
	cin => \inst|cnt[16]~167\,
	combout => \inst|cnt[17]~168_combout\,
	cout => \inst|cnt[17]~169\);

\inst|cnt[18]~170\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|cnt[18]~170_combout\ = \inst|cnt\(18) & !\inst|cnt[17]~169\ # !\inst|cnt\(18) & (\inst|cnt[17]~169\ # GND)
-- \inst|cnt[18]~171\ = CARRY(!\inst|cnt[17]~169\ # !\inst|cnt\(18))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|cnt\(18),
	datad => VCC,
	cin => \inst|cnt[17]~169\,
	combout => \inst|cnt[18]~170_combout\,
	cout => \inst|cnt[18]~171\);

\inst|cnt[20]~174\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|cnt[20]~174_combout\ = \inst|cnt\(20) & !\inst|cnt[19]~173\ # !\inst|cnt\(20) & (\inst|cnt[19]~173\ # GND)
-- \inst|cnt[20]~175\ = CARRY(!\inst|cnt[19]~173\ # !\inst|cnt\(20))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|cnt\(20),
	datad => VCC,
	cin => \inst|cnt[19]~173\,
	combout => \inst|cnt[20]~174_combout\,
	cout => \inst|cnt[20]~175\);

\inst2|cnt[4]~92\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst2|cnt[4]~92_combout\ = \inst2|cnt\(4) & !\inst2|cnt[3]~91\ # !\inst2|cnt\(4) & (\inst2|cnt[3]~91\ # GND)
-- \inst2|cnt[4]~93\ = CARRY(!\inst2|cnt[3]~91\ # !\inst2|cnt\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|cnt\(4),
	datad => VCC,
	cin => \inst2|cnt[3]~91\,
	combout => \inst2|cnt[4]~92_combout\,
	cout => \inst2|cnt[4]~93\);

\inst2|LessThan0~108\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst2|LessThan0~108_combout\ = \inst2|cnt\(4) # \inst2|cnt\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst2|cnt\(4),
	datac => \inst2|cnt\(5),
	combout => \inst2|LessThan0~108_combout\);

\inst1|FSK_out~clkctrl\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \inst1|FSK_out~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst1|FSK_out~clkctrl_outclk\);

\clk~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\inst2|cnt[1]~86\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst2|cnt[1]~86_combout\ = \inst2|cnt\(0) & (\inst2|cnt\(1) $ VCC) # !\inst2|cnt\(0) & \inst2|cnt\(1) & VCC
-- \inst2|cnt[1]~87\ = CARRY(\inst2|cnt\(0) & \inst2|cnt\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110011010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst2|cnt\(0),
	datab => \inst2|cnt\(1),
	datad => VCC,
	combout => \inst2|cnt[1]~86_combout\,
	cout => \inst2|cnt[1]~87\);

\inst2|cnt[1]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~combout\,
	datain => \inst2|cnt[1]~86_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst2|cnt\(1));

\inst2|cnt[2]~88\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst2|cnt[2]~88_combout\ = \inst2|cnt\(2) & !\inst2|cnt[1]~87\ # !\inst2|cnt\(2) & (\inst2|cnt[1]~87\ # GND)
-- \inst2|cnt[2]~89\ = CARRY(!\inst2|cnt[1]~87\ # !\inst2|cnt\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on