fsk.fit.rpt

通信系统的FSK调制程序

; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/My_Design/FPGA/FSK/FSK.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 39 / 4,608 ( < 1 % ) ;
;     -- Combinational with no register       ; 12                   ;
;     -- Register only                        ; 0                    ;
;     -- Combinational with a register        ; 27                   ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 3                    ;
;     -- 3 input functions                    ; 5                    ;
;     -- <=2 input functions                  ; 31                   ;
;     -- Register only                        ; 0                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 12                   ;
;     -- arithmetic mode                      ; 27                   ;
;                                             ;                      ;
; Total registers*                            ; 27 / 5,010 ( < 1 % ) ;
;     -- Dedicated logic registers            ; 27 / 4,608 ( < 1 % ) ;
;     -- I/O registers                        ; 0 / 402 ( 0 % )      ;
;                                             ;                      ;
; Total LABs:  partially or completely used   ; 3 / 288 ( 1 % )      ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 5 / 142 ( 4 % )      ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )       ;
; Global signals                              ; 2                    ;
; M4Ks                                        ; 0 / 26 ( 0 % )       ;
; Total memory bits                           ; 0 / 119,808 ( 0 % )  ;
; Total RAM block bits                        ; 0 / 119,808 ( 0 % )  ;
; Embedded Multiplier 9-bit elements          ; 0 / 26 ( 0 % )       ;
; PLLs                                        ; 0 / 2 ( 0 % )        ;
; Global clocks                               ; 2 / 8 ( 25 % )       ;
; Average interconnect usage                  ; 0%                   ;
; Peak interconnect usage                     ; 0%                   ;
; Maximum fan-out node                        ; clk~clkctrl          ;
; Maximum fan-out                             ; 15                   ;
; Highest non-global fan-out signal           ; clk                  ;
; Highest non-global fan-out                  ; 9                    ;
; Total fan-out                               ; 145                  ;
; Average fan-out                             ; 1.93                 ;
+---------------------------------------------+----------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                     ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Base_Sin ; 14    ; 1        ; 0            ; 11           ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
; clk      ; 132   ; 3        ; 28           ; 7            ; 0           ; 10                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                              ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Demod   ; 99    ; 4        ; 24           ; 0            ; 0           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; Fitter               ; 0 pF ;
; FSK_out ; 31    ; 1        ; 0            ; 5            ; 1           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; Fitter               ; 0 pF ;
; led     ; 108   ; 3        ; 28           ; 2            ; 0           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; User                 ; 0 pF ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+


+-----------------------------------------------------------+
; I/O Bank Usage                                            ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1        ; 4 / 34 ( 12 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 35 ( 0 % )  ; 3.3V          ; --           ;
; 3        ; 2 / 37 ( 5 % )  ; 3.3V          ; --           ;
; 4        ; 1 / 36 ( 3 % )  ; 3.3V          ; --           ;