ex7.vhd

来自「vhdl基本门电路」· VHDL 代码 · 共 21 行

include "ex3.inc"
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ex7 IS
		PORT(
		D,CLK       	: IN	STD_LOGIC;
		Q       	: OUT	STD_LOGIC);
END ex7;
ARCHITECTURE a OF ex7 is
	SIGNAL temp : STD_LOGIC;
  BEGIN
   PROCESS(CLK)
     BEGIN         
         temp<=D;
        IF CLK'EVENT AND CLK='1' THEN
          Q<=TEMP;    
 	     END IF;
   END PROCESS;
END a;