ex81.vhd

vhdl基本门电路

LIBRARY IEEE;
USE    IEEE.STD_LOGIC_1164.ALL;
USE    IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY EX81 IS
     PORT(
           D     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
           OEN,G : IN  STD_LOGIC;
           Q     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
          );
END EX81; 
ARCHITECTURE A  OF EX81 IS
     SIGNAL  TEMP :STD_LOGIC_VECTOR(7 DOWNTO 0);
 BEGIN
    PROCESS 
       BEGIN
       IF OEN='0' THEN 
          Q<=TEMP;
          ELSE Q<="ZZZZZZZZ";
       END IF;
       IF G='1' THEN 
           TEMP<=D;
       END IF; 
    END PROCESS;    
END A;