lh.vhd

来自「vhdl基本门电路」· VHDL 代码 · 共 47 行

-- 元件定义语句
-- COMPONENT 元件名 is           
-- generic (类属)
-- port (端口)
-- end COMPONENT 
---------------------
-- 元件例化语句
-- 元件名 port map (
--            [端口名=>] 连接端口名，...);
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity nd2 is
  PORT(
         A,B : IN STD_LOGIC;
          C  :OUT STD_LOGIC);
   END ND2;
ARCHITECTURE A OF nd2
 BEGIN
     C<=A AND B;
END A;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity nd41 is
PORT(
         A,B : IN STD_LOGIC;
          C  :OUT STD_LOGIC);
   END ND41;
ARCHITECTURE AB OF ND41
COMPONENT ND2
      PORT(
         A,B : IN STD_LOGIC;
          C  :OUT STD_LOGIC);
END COMPONENT;
SIGNAL  X,Y:STD_LOGIC;
  BEGIN
     U1:ND2 PORT MAP(A1,B1,X);
     U2:ND2 PORT MAP(A=>C1,C=>Y,B=>D1);
     U3:ND2 PORT MAP(X,Y,C=>Z);


END ARCHITECTURE AB;