usea74.rpt

vhdl基本门电路

usea74

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC23 Q1
        | +------------- LC27 Q2
        | | +----------- LC22 Q3
        | | | +--------- LC24 Q4
        | | | | +------- LC21 Q5
        | | | | | +----- LC19 Q6
        | | | | | | +--- LC18 Q7
        | | | | | | | +- LC17 Q8
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC23 -> * - - - - - - - | - * | <-- Q1
LC27 -> - * - - - - - - | - * | <-- Q2
LC22 -> - - * - - - - - | - * | <-- Q3
LC24 -> - - - * - - - - | - * | <-- Q4
LC21 -> - - - - * - - - | - * | <-- Q5
LC19 -> - - - - - * - - | - * | <-- Q6
LC18 -> - - - - - - * - | - * | <-- Q7
LC17 -> - - - - - - - * | - * | <-- Q8

Pin
4    -> * - - - - - - - | - * | <-- D1
11   -> - * - - - - - - | - * | <-- D2
12   -> - - * - - - - - | - * | <-- D3
14   -> - - - * - - - - | - * | <-- D4
16   -> - - - - * - - - | - * | <-- D5
9    -> - - - - - * - - | - * | <-- D6
8    -> - - - - - - * - | - * | <-- D7
6    -> - - - - - - - * | - * | <-- D8
5    -> * * * * * * * * | - * | <-- G
44   -> - - - - - - - - | - - | <-- OEN


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             d:\vhdl_ex\usea74.rpt
usea74

** EQUATIONS **

D1       : INPUT;
D2       : INPUT;
D3       : INPUT;
D4       : INPUT;
D5       : INPUT;
D6       : INPUT;
D7       : INPUT;
D8       : INPUT;
G        : INPUT;
OEN      : INPUT;

-- Node name is 'Q1' = '|74373:AAA|:12' 
-- Equation name is 'Q1', type is output 
Q1       = TRI(_LC023, GLOBAL(!OEN));
_LC023   = LCELL( _EQ001 $  GND);
  _EQ001 =  D1 &  G
         #  D1 &  _LC023
         # !G &  _LC023;

-- Node name is 'Q2' = '|74373:AAA|:13' 
-- Equation name is 'Q2', type is output 
Q2       = TRI(_LC027, GLOBAL(!OEN));
_LC027   = LCELL( _EQ002 $  GND);
  _EQ002 =  D2 &  G
         #  D2 &  _LC027
         # !G &  _LC027;

-- Node name is 'Q3' = '|74373:AAA|:14' 
-- Equation name is 'Q3', type is output 
Q3       = TRI(_LC022, GLOBAL(!OEN));
_LC022   = LCELL( _EQ003 $  GND);
  _EQ003 =  D3 &  G
         #  D3 &  _LC022
         # !G &  _LC022;

-- Node name is 'Q4' = '|74373:AAA|:15' 
-- Equation name is 'Q4', type is output 
Q4       = TRI(_LC024, GLOBAL(!OEN));
_LC024   = LCELL( _EQ004 $  GND);
  _EQ004 =  D4 &  G
         #  D4 &  _LC024
         # !G &  _LC024;

-- Node name is 'Q5' = '|74373:AAA|:16' 
-- Equation name is 'Q5', type is output 
Q5       = TRI(_LC021, GLOBAL(!OEN));
_LC021   = LCELL( _EQ005 $  GND);
  _EQ005 =  D5 &  G
         #  D5 &  _LC021
         # !G &  _LC021;

-- Node name is 'Q6' = '|74373:AAA|:17' 
-- Equation name is 'Q6', type is output 
Q6       = TRI(_LC019, GLOBAL(!OEN));
_LC019   = LCELL( _EQ006 $  GND);
  _EQ006 =  D6 &  G
         #  D6 &  _LC019
         # !G &  _LC019;

-- Node name is 'Q7' = '|74373:AAA|:18' 
-- Equation name is 'Q7', type is output 
Q7       = TRI(_LC018, GLOBAL(!OEN));
_LC018   = LCELL( _EQ007 $  GND);
  _EQ007 =  D7 &  G
         #  D7 &  _LC018
         # !G &  _LC018;

-- Node name is 'Q8' = '|74373:AAA|:19' 
-- Equation name is 'Q8', type is output 
Q8       = TRI(_LC017, GLOBAL(!OEN));
_LC017   = LCELL( _EQ008 $  GND);
  _EQ008 =  D8 &  G
         #  D8 &  _LC017
         # !G &  _LC017;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                      d:\vhdl_ex\usea74.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,376K