ctrdel.vhd

来自「vhdl基本门电路」· VHDL 代码 · 共 30 行

library ieee;
use ieee.STD_LOGIC_1164.ALL;
entity CTRDEL is
    generic (CLRDEL: TIME := 10 ns; CLKDEL: TIME := 15 ns);
    port      (EN, CLR, CLK : in BIT; 
		      COUT : out BIT_VECTOR(3 downto 0));
end CTRDEL;

architecture BEHAV of CTRDEL is
begin
    CNT: process(CLK, CLR)
        variable COUNT: BIT_VECTOR(3 downto 0) := "0000";
    begin
        if CLR = '1' then
            COUNT := "0000";
            COUT <= "0000" after CLRDEL;
        elsif en = '1' and CLK'EVENT and (CLK='1') then
 
            for I in 0 to 3 loop
                if COUNT(I) = '0' then
                    COUNT(I) := '1';
                    exit;
                else 
                    COUNT(I) := '0';
                end if;
            end loop;
            COUT <= COUNT after CLKDEL;
        end if;
    end process CNT;