mb.rpt

vhdl基本门电路

  _EQ046 =  _LC008 &  _LC013 &  _LC027 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC002', type is buried 
_LC002   = LCELL( _LC028 $  _EQ047);
  _EQ047 =  _LC006 &  _LC008 &  _LC013 &  _LC027 &  _LC056 &  _LC058 & 
              _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried 
_LC045   = LCELL( _LC029 $  _EQ048);
  _EQ048 =  _LC006 &  _LC008 &  _LC013 &  _LC027 &  _LC028 &  _LC056 & 
              _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC039', type is buried 
_LC039   = LCELL( _LC018 $  _EQ049);
  _EQ049 =  _LC006 &  _LC008 &  _LC013 &  _LC027 &  _LC028 &  _LC029 & 
              _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC042', type is buried 
_LC042   = LCELL( _LC026 $  _EQ050);
  _EQ050 =  _LC006 &  _LC008 &  _LC013 &  _LC018 &  _LC027 &  _LC028 & 
              _LC029 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC044', type is buried 
_LC044   = LCELL( _LC023 $  _EQ051);
  _EQ051 =  _LC006 &  _LC008 &  _LC013 &  _LC018 &  _LC026 &  _LC027 & 
              _LC028 &  _LC029 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried 
_LC047   = LCELL( _LC022 $  _EQ052);
  _EQ052 =  _LC006 &  _LC008 &  _LC013 &  _LC018 &  _LC023 &  _LC026 & 
              _LC027 &  _LC028 &  _LC029 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC048', type is buried 
_LC048   = LCELL( _LC032 $  _EQ053);
  _EQ053 =  _LC006 &  _LC008 &  _LC013 &  _LC018 &  _LC022 &  _LC023 & 
              _LC026 &  _LC027 &  _LC028 &  _LC029 &  _LC056 &  _LC058 & 
              _LC061;

-- Node name is '|CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC043', type is buried 
_LC043   = LCELL( _LC034 $  _EQ054);
  _EQ054 =  _LC006 &  _LC008 &  _LC013 &  _LC018 &  _LC022 &  _LC023 & 
              _LC026 &  _LC027 &  _LC028 &  _LC029 &  _LC032 &  _LC056 & 
              _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:17' = '|CLKGEN:4|TEMP0' 
-- Equation name is '_LC061', type is buried 
_LC061   = TFFE( VCC, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is '|CLKGEN:4|:16' = '|CLKGEN:4|TEMP1' 
-- Equation name is '_LC058', type is buried 
_LC058   = TFFE( _LC061, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is '|CLKGEN:4|:15' = '|CLKGEN:4|TEMP2' 
-- Equation name is '_LC056', type is buried 
_LC056   = TFFE( _EQ055, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ055 =  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:14' = '|CLKGEN:4|TEMP3' 
-- Equation name is '_LC013', type is buried 
_LC013   = DFFE( _EQ056 $  _LC060, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ056 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC056 &  _LC058 &  _LC060 &  _LC061;

-- Node name is '|CLKGEN:4|:13' = '|CLKGEN:4|TEMP4' 
-- Equation name is '_LC008', type is buried 
_LC008   = DFFE( _EQ057 $  _LC055, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ057 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC055 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:12' = '|CLKGEN:4|TEMP5' 
-- Equation name is '_LC027', type is buried 
_LC027   = DFFE( _EQ058 $  _LC050, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ058 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC050 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:11' = '|CLKGEN:4|TEMP6' 
-- Equation name is '_LC006', type is buried 
_LC006   = DFFE( _EQ059 $  _LC003, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ059 =  _LC003 & !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & 
             !_LC023 &  _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 & 
              _LC034 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:10' = '|CLKGEN:4|TEMP7' 
-- Equation name is '_LC028', type is buried 
_LC028   = DFFE( _EQ060 $  _LC002, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ060 =  _LC002 & !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & 
             !_LC023 &  _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 & 
              _LC034 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:9' = '|CLKGEN:4|TEMP8' 
-- Equation name is '_LC029', type is buried 
_LC029   = DFFE( _EQ061 $  _LC045, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ061 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC045 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:8' = '|CLKGEN:4|TEMP9' 
-- Equation name is '_LC018', type is buried 
_LC018   = DFFE( _EQ062 $  _LC039, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ062 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC039 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:7' = '|CLKGEN:4|TEMP10' 
-- Equation name is '_LC026', type is buried 
_LC026   = DFFE( _EQ063 $  _LC042, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ063 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC042 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:6' = '|CLKGEN:4|TEMP11' 
-- Equation name is '_LC023', type is buried 
_LC023   = DFFE( _EQ064 $  _LC044, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ064 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC044 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:5' = '|CLKGEN:4|TEMP12' 
-- Equation name is '_LC022', type is buried 
_LC022   = DFFE( _EQ065 $  _LC047, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ065 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC047 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:4' = '|CLKGEN:4|TEMP13' 
-- Equation name is '_LC032', type is buried 
_LC032   = DFFE( _EQ066 $  _LC048, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ066 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC048 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CLKGEN:4|:3' = '|CLKGEN:4|TEMP14' 
-- Equation name is '_LC034', type is buried 
_LC034   = DFFE( _EQ067 $  _LC043, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ067 = !_LC006 & !_LC008 &  _LC013 & !_LC018 &  _LC022 & !_LC023 & 
              _LC026 &  _LC027 & !_LC028 &  _LC029 &  _LC032 &  _LC034 & 
              _LC043 &  _LC056 &  _LC058 &  _LC061;

-- Node name is '|CNT6:6|LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC038', type is buried 
_LC038   = LCELL( Q23 $  _EQ068);
  _EQ068 =  Q20 &  Q21 &  Q22;

-- Node name is '|CNT6:8|LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC059', type is buried 
_LC059   = LCELL( Q15 $  _EQ069);
  _EQ069 =  Q12 &  Q13 &  Q14;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                               d:\mb\mb.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,367K