vhdl10.map.rpt

程序提供了一种简单高效的模拟交通灯控制器的算法

;     -- Register only                        ; 0       ;
;     -- Combinational with a register        ; 3       ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 8       ;
;     -- 3 input functions                    ; 6       ;
;     -- 2 input functions                    ; 0       ;
;     -- 1 input functions                    ; 0       ;
;     -- 0 input functions                    ; 0       ;
;         -- Combinational cells for routing  ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 14      ;
;     -- arithmetic mode                      ; 0       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 3       ;
; I/O pins                                    ; 8       ;
; Maximum fan-out node                        ; time[0] ;
; Maximum fan-out                             ; 7       ;
; Total fan-out                               ; 56      ;
; Average fan-out                             ; 2.55    ;
+---------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |vhdl10                    ; 14 (14)     ; 3            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 8    ; 0            ; 11 (11)      ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |vhdl10             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; State Machine - |vhdl10|c_st                      ;
+-------------+-------------+------------+----------+
; Name        ; c_st.yellow ; c_st.green ; c_st.red ;
+-------------+-------------+------------+----------+
; c_st.red    ; 0           ; 0          ; 0        ;
; c_st.green  ; 0           ; 1          ; 1        ;
; c_st.yellow ; 1           ; 0          ; 1        ;
+-------------+-------------+------------+----------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; output[0]$latch                                    ; Selector6           ; yes                    ;
; output[1]$latch                                    ; Selector6           ; yes                    ;
; output[2]$latch                                    ; Selector6           ; yes                    ;
; Number of user-specified and inferred latches = 3  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; c_st.red                               ; 5       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------+
; Source assignments for Top-level Entity: |Vhdl10 ;
+----------------+-------+------+------------------+
; Assignment     ; Value ; From ; To               ;
+----------------+-------+------+------------------+
; POWER_UP_LEVEL ; Low   ; -    ; c_st.yellow      ;
; POWER_UP_LEVEL ; Low   ; -    ; c_st.green       ;
; POWER_UP_LEVEL ; High  ; -    ; c_st.red         ;
+----------------+-------+------+------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jan 07 02:09:08 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Vhdl10 -c Vhdl10
Info: Found 2 design units, including 1 entities, in source file ../Vhdl10.vhd
    Info: Found design unit 1: vhdl10-one
    Info: Found entity 1: vhdl10
Info: Elaborating entity "Vhdl10" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at Vhdl10.vhd(24): inferring latch(es) for signal or variable "output", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at Vhdl10.vhd(24): inferred latch for "output[0]"
Info (10041): Verilog HDL or VHDL info at Vhdl10.vhd(24): inferred latch for "output[1]"
Info (10041): Verilog HDL or VHDL info at Vhdl10.vhd(24): inferred latch for "output[2]"
Info: State machine "|vhdl10|c_st" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|vhdl10|c_st"
Info: Encoding result for state machine "|vhdl10|c_st"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "c_st.yellow"
        Info: Encoded state bit "c_st.green"
        Info: Encoded state bit "c_st.red"
    Info: State "|vhdl10|c_st.red" uses code string "000"
    Info: State "|vhdl10|c_st.green" uses code string "011"
    Info: State "|vhdl10|c_st.yellow" uses code string "101"
Warning: Latch output[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_st.red
Warning: Latch output[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_st.green
Info: Implemented 22 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 3 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Mon Jan 07 02:09:10 2008
    Info: Elapsed time: 00:00:02