vhdl10.tan.rpt

程序提供了一种简单高效的模拟交通灯控制器的算法

; N/A   ; None         ; 11.496 ns  ; output[2]$latch ; output[2] ; time[2]    ;
; N/A   ; None         ; 11.358 ns  ; output[1]$latch ; output[1] ; time[0]    ;
; N/A   ; None         ; 11.026 ns  ; output[0]$latch ; output[0] ; time[1]    ;
; N/A   ; None         ; 11.017 ns  ; output[0]$latch ; output[0] ; time[2]    ;
; N/A   ; None         ; 10.897 ns  ; output[2]$latch ; output[2] ; time[0]    ;
; N/A   ; None         ; 10.418 ns  ; output[0]$latch ; output[0] ; time[0]    ;
+-------+--------------+------------+-----------------+-----------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+---------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To          ; To Clock ;
+---------------+-------------+-----------+---------+-------------+----------+
; N/A           ; None        ; 0.100 ns  ; time[2] ; c_st.yellow ; clk      ;
; N/A           ; None        ; 0.091 ns  ; time[1] ; c_st.yellow ; clk      ;
; N/A           ; None        ; -0.097 ns ; time[2] ; c_st.green  ; clk      ;
; N/A           ; None        ; -0.106 ns ; time[1] ; c_st.green  ; clk      ;
; N/A           ; None        ; -0.377 ns ; time[2] ; c_st.red    ; clk      ;
; N/A           ; None        ; -0.508 ns ; time[1] ; c_st.red    ; clk      ;
; N/A           ; None        ; -0.576 ns ; time[0] ; c_st.red    ; clk      ;
; N/A           ; None        ; -2.362 ns ; time[0] ; c_st.yellow ; clk      ;
; N/A           ; None        ; -2.366 ns ; time[0] ; c_st.green  ; clk      ;
; N/A           ; None        ; -2.820 ns ; reset   ; c_st.yellow ; clk      ;
; N/A           ; None        ; -2.821 ns ; reset   ; c_st.red    ; clk      ;
; N/A           ; None        ; -2.826 ns ; reset   ; c_st.green  ; clk      ;
+---------------+-------------+-----------+---------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jan 07 02:09:22 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Vhdl10 -c Vhdl10 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "output[0]$latch" is a latch
    Warning: Node "output[1]$latch" is a latch
    Warning: Node "output[2]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "time[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "time[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "time[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Selector6~139" as buffer
    Info: Detected gated clock "Selector6~138" as buffer
    Info: Detected ripple clock "c_st.green" as buffer
    Info: Detected gated clock "c_st~223" as buffer
    Info: Detected gated clock "Equal2~26" as buffer
    Info: Detected ripple clock "c_st.red" as buffer
    Info: Detected gated clock "c_st~224" as buffer
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "c_st.red" and destination register "c_st.red"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.347 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
            Info: 2: + IC(0.555 ns) + CELL(0.075 ns) = 0.630 ns; Loc. = LC_X18_Y30_N2; Fanout = 1; COMB Node = 'c_st~227'
            Info: 3: + IC(0.494 ns) + CELL(0.223 ns) = 1.347 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
            Info: Total cell delay = 0.298 ns ( 22.12 % )
            Info: Total interconnect delay = 1.049 ns ( 77.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.923 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
                Info: Total cell delay = 1.370 ns ( 46.87 % )
                Info: Total interconnect delay = 1.553 ns ( 53.13 % )
            Info: - Longest clock path from clock "clk" to source register is 2.923 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
                Info: Total cell delay = 1.370 ns ( 46.87 % )
                Info: Total interconnect delay = 1.553 ns ( 53.13 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Warning: Circuit may not operate. Detected 3 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "c_st.green" and destination pin or register "output[2]$latch" for clock "clk" (Hold time is 4.819 ns)
    Info: + Largest clock skew is 5.662 ns
        Info: + Longest clock path from clock "clk" to destination register is 8.585 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(1.553 ns) + CELL(0.698 ns) = 3.079 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
            Info: 3: + IC(0.398 ns) + CELL(0.075 ns) = 3.552 ns; Loc. = LC_X17_Y30_N9; Fanout = 2; COMB Node = 'c_st~223'
            Info: 4: + IC(0.498 ns) + CELL(0.183 ns) = 4.233 ns; Loc. = LC_X18_Y30_N3; Fanout = 1; COMB Node = 'Selector6~138'
            Info: 5: + IC(0.327 ns) + CELL(0.183 ns) = 4.743 ns; Loc. = LC_X18_Y30_N6; Fanout = 3; COMB Node = 'Selector6~139'
            Info: 6: + IC(3.659 ns) + CELL(0.183 ns) = 8.585 ns; Loc. = LC_X17_Y30_N4; Fanout = 1; REG Node = 'output[2]$latch'
            Info: Total cell delay = 2.150 ns ( 25.04 % )
            Info: Total interconnect delay = 6.435 ns ( 74.96 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.923 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N0; Fanout = 4; REG Node = 'c_st.green'
            Info: Total cell delay = 1.370 ns ( 46.87 % )
            Info: Total interconnect delay = 1.553 ns ( 53.13 % )
    Info: - Micro clock to output delay of source is 0.156 ns
    Info: - Shortest register to register delay is 0.687 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N0; Fanout = 4; REG Node = 'c_st.green'
        Info: 2: + IC(0.407 ns) + CELL(0.280 ns) = 0.687 ns; Loc. = LC_X17_Y30_N4; Fanout = 1; REG Node = 'output[2]$latch'
        Info: Total cell delay = 0.280 ns ( 40.76 % )
        Info: Total interconnect delay = 0.407 ns ( 59.24 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "c_st.red" (data pin = "time[2]", clock pin = "clk") is 3.011 ns
    Info: + Longest pin to register delay is 5.924 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C15; Fanout = 6; CLK Node = 'time[2]'
        Info: 2: + IC(3.937 ns) + CELL(0.183 ns) = 5.207 ns; Loc. = LC_X18_Y30_N2; Fanout = 1; COMB Node = 'c_st~227'
        Info: 3: + IC(0.494 ns) + CELL(0.223 ns) = 5.924 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
        Info: Total cell delay = 1.493 ns ( 25.20 % )
        Info: Total interconnect delay = 4.431 ns ( 74.80 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.923 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
        Info: Total cell delay = 1.370 ns ( 46.87 % )
        Info: Total interconnect delay = 1.553 ns ( 53.13 % )
Info: tco from clock "clk" to destination pin "output[1]" through register "output[1]$latch" is 12.944 ns
    Info: + Longest clock path from clock "clk" to source register is 8.479 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(1.553 ns) + CELL(0.698 ns) = 3.079 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'
        Info: 3: + IC(0.398 ns) + CELL(0.075 ns) = 3.552 ns; Loc. = LC_X17_Y30_N9; Fanout = 2; COMB Node = 'c_st~223'
        Info: 4: + IC(0.498 ns) + CELL(0.183 ns) = 4.233 ns; Loc. = LC_X18_Y30_N3; Fanout = 1; COMB Node = 'Selector6~138'
        Info: 5: + IC(0.327 ns) + CELL(0.183 ns) = 4.743 ns; Loc. = LC_X18_Y30_N6; Fanout = 3; COMB Node = 'Selector6~139'
        Info: 6: + IC(3.661 ns) + CELL(0.075 ns) = 8.479 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'output[1]$latch'
        Info: Total cell delay = 2.042 ns ( 24.08 % )
        Info: Total interconnect delay = 6.437 ns ( 75.92 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.465 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'output[1]$latch'
        Info: 2: + IC(2.061 ns) + CELL(2.404 ns) = 4.465 ns; Loc. = PIN_E14; Fanout = 0; PIN Node = 'output[1]'
        Info: Total cell delay = 2.404 ns ( 53.84 % )
        Info: Total interconnect delay = 2.061 ns ( 46.16 % )
Info: th for register "c_st.yellow" (data pin = "time[2]", clock pin = "clk") is 0.100 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.923 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N6; Fanout = 3; REG Node = 'c_st.yellow'
        Info: Total cell delay = 1.370 ns ( 46.87 % )
        Info: Total interconnect delay = 1.553 ns ( 53.13 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 2.923 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C15; Fanout = 6; CLK Node = 'time[2]'
        Info: 2: + IC(1.199 ns) + CELL(0.280 ns) = 2.566 ns; Loc. = LC_X17_Y30_N5; Fanout = 2; COMB Node = 'c_st~224'
        Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 2.923 ns; Loc. = LC_X17_Y30_N6; Fanout = 3; REG Node = 'c_st.yellow'
        Info: Total cell delay = 1.590 ns ( 54.40 % )
        Info: Total interconnect delay = 1.333 ns ( 45.60 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 7 warnings
    Info: Processing ended: Mon Jan 07 02:09:23 2008
    Info: Elapsed time: 00:00:01