📄 vhdl10.tan.rpt
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Timing Analyzer report for Vhdl10
Mon Jan 07 02:09:23 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. Clock Hold: 'clk'
7. tsu
8. tco
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.011 ns ; time[2] ; c_st.red ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 12.944 ns ; output[1]$latch ; output[1] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.100 ns ; time[2] ; c_st.yellow ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; c_st.red ; c_st.red ; clk ; clk ; 0 ;
; Clock Hold: 'clk' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; c_st.green ; output[2]$latch ; clk ; clk ; 3 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 3 ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; time[2] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; time[1] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; time[0] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; c_st.red ; c_st.red ; clk ; clk ; None ; None ; 1.347 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; c_st.green ; c_st.green ; clk ; clk ; None ; None ; 1.147 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; c_st.yellow ; c_st.yellow ; clk ; clk ; None ; None ; 1.129 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; c_st.red ; c_st.green ; clk ; clk ; None ; None ; 1.028 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; c_st.green ; c_st.yellow ; clk ; clk ; None ; None ; 0.853 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; c_st.yellow ; c_st.red ; clk ; clk ; None ; None ; 0.844 ns ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk' ;
+------------------------------------------+-------------+-----------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+-------------+-----------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; c_st.green ; output[2]$latch ; clk ; clk ; None ; None ; 0.687 ns ;
; Not operational: Clock Skew > Data Delay ; c_st.red ; output[1]$latch ; clk ; clk ; None ; None ; 0.778 ns ;
; Not operational: Clock Skew > Data Delay ; c_st.yellow ; output[0]$latch ; clk ; clk ; None ; None ; 1.057 ns ;
+------------------------------------------+-------------+-----------------+------------+----------+----------------------------+----------------------------+--------------------------+
+----------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+---------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+---------+-------------+----------+
; N/A ; None ; 3.011 ns ; time[2] ; c_st.red ; clk ;
; N/A ; None ; 3.007 ns ; time[0] ; c_st.red ; clk ;
; N/A ; None ; 2.936 ns ; reset ; c_st.green ; clk ;
; N/A ; None ; 2.931 ns ; reset ; c_st.red ; clk ;
; N/A ; None ; 2.930 ns ; reset ; c_st.yellow ; clk ;
; N/A ; None ; 2.926 ns ; time[2] ; c_st.green ; clk ;
; N/A ; None ; 2.922 ns ; time[2] ; c_st.yellow ; clk ;
; N/A ; None ; 2.883 ns ; time[0] ; c_st.green ; clk ;
; N/A ; None ; 2.854 ns ; time[1] ; c_st.red ; clk ;
; N/A ; None ; 2.836 ns ; time[1] ; c_st.yellow ; clk ;
; N/A ; None ; 2.805 ns ; time[0] ; c_st.yellow ; clk ;
; N/A ; None ; 2.763 ns ; time[1] ; c_st.green ; clk ;
+-------+--------------+------------+---------+-------------+----------+
+------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------+-----------+------------+
; N/A ; None ; 12.944 ns ; output[1]$latch ; output[1] ; clk ;
; N/A ; None ; 12.483 ns ; output[2]$latch ; output[2] ; clk ;
; N/A ; None ; 12.004 ns ; output[0]$latch ; output[0] ; clk ;
; N/A ; None ; 11.966 ns ; output[1]$latch ; output[1] ; time[1] ;
; N/A ; None ; 11.957 ns ; output[1]$latch ; output[1] ; time[2] ;
; N/A ; None ; 11.505 ns ; output[2]$latch ; output[2] ; time[1] ;
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