vhdl10.map.qmsg

程序提供了一种简单高效的模拟交通灯控制器的算法

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 07 02:09:08 2008 " "Info: Processing started: Mon Jan 07 02:09:08 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Vhdl10 -c Vhdl10 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Vhdl10 -c Vhdl10" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Vhdl10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../Vhdl10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vhdl10-one " "Info: Found design unit 1: vhdl10-one" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vhdl10 " "Info: Found entity 1: vhdl10" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Vhdl10 " "Info: Elaborating entity \"Vhdl10\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "output Vhdl10.vhd(24) " "Warning (10631): VHDL Process Statement warning at Vhdl10.vhd(24): inferring latch(es) for signal or variable \"output\", which holds its previous value in one or more paths through the process" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "output\[0\] Vhdl10.vhd(24) " "Info (10041): Verilog HDL or VHDL info at Vhdl10.vhd(24): inferred latch for \"output\[0\]\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "output\[1\] Vhdl10.vhd(24) " "Info (10041): Verilog HDL or VHDL info at Vhdl10.vhd(24): inferred latch for \"output\[1\]\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "output\[2\] Vhdl10.vhd(24) " "Info (10041): Verilog HDL or VHDL info at Vhdl10.vhd(24): inferred latch for \"output\[2\]\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|vhdl10\|c_st 3 " "Info: State machine \"\|vhdl10\|c_st\" contains 3 states" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|vhdl10\|c_st " "Info: Selected Auto state machine encoding method for state machine \"\|vhdl10\|c_st\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|vhdl10\|c_st " "Info: Encoding result for state machine \"\|vhdl10\|c_st\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "c_st.yellow " "Info: Encoded state bit \"c_st.yellow\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "c_st.green " "Info: Encoded state bit \"c_st.green\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "c_st.red " "Info: Encoded state bit \"c_st.red\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vhdl10\|c_st.red 000 " "Info: State \"\|vhdl10\|c_st.red\" uses code string \"000\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vhdl10\|c_st.green 011 " "Info: State \"\|vhdl10\|c_st.green\" uses code string \"011\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vhdl10\|c_st.yellow 101 " "Info: State \"\|vhdl10\|c_st.yellow\" uses code string \"101\"" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "output\[1\]\$latch " "Warning: Latch output\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_st.red " "Warning: Ports D and ENA on the latch are fed by the same signal c_st.red" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "output\[2\]\$latch " "Warning: Latch output\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_st.green " "Warning: Ports D and ENA on the latch are fed by the same signal c_st.green" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "22 " "Info: Implemented 22 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 07 02:09:10 2008 " "Info: Processing ended: Mon Jan 07 02:09:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}