vhdl10.tan.qmsg

来自「程序提供了一种简单高效的模拟交通灯控制器的算法」· QMSG 代码 · 共 14 行 · 第 1/4 页

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "c_st.green output\[2\]\$latch clk 4.819 ns " "Info: Found hold time violation between source  pin or register \"c_st.green\" and destination pin or register \"output\[2\]\$latch\" for clock \"clk\" (Hold time is 4.819 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.662 ns + Largest " "Info: + Largest clock skew is 5.662 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.585 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.585 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.698 ns) 3.079 ns c_st.red 2 REG LC_X17_Y30_N8 5 " "Info: 2: + IC(1.553 ns) + CELL(0.698 ns) = 3.079 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.251 ns" { clk c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.075 ns) 3.552 ns c_st~223 3 COMB LC_X17_Y30_N9 2 " "Info: 3: + IC(0.398 ns) + CELL(0.075 ns) = 3.552 ns; Loc. = LC_X17_Y30_N9; Fanout = 2; COMB Node = 'c_st~223'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.473 ns" { c_st.red c_st~223 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.183 ns) 4.233 ns Selector6~138 4 COMB LC_X18_Y30_N3 1 " "Info: 4: + IC(0.498 ns) + CELL(0.183 ns) = 4.233 ns; Loc. = LC_X18_Y30_N3; Fanout = 1; COMB Node = 'Selector6~138'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.681 ns" { c_st~223 Selector6~138 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.183 ns) 4.743 ns Selector6~139 5 COMB LC_X18_Y30_N6 3 " "Info: 5: + IC(0.327 ns) + CELL(0.183 ns) = 4.743 ns; Loc. = LC_X18_Y30_N6; Fanout = 3; COMB Node = 'Selector6~139'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.510 ns" { Selector6~138 Selector6~139 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.659 ns) + CELL(0.183 ns) 8.585 ns output\[2\]\$latch 6 REG LC_X17_Y30_N4 1 " "Info: 6: + IC(3.659 ns) + CELL(0.183 ns) = 8.585 ns; Loc. = LC_X17_Y30_N4; Fanout = 1; REG Node = 'output\[2\]\$latch'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.842 ns" { Selector6~139 output[2]$latch } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.150 ns ( 25.04 % ) " "Info: Total cell delay = 2.150 ns ( 25.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.435 ns ( 74.96 % ) " "Info: Total interconnect delay = 6.435 ns ( 74.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.585 ns" { clk c_st.red c_st~223 Selector6~138 Selector6~139 output[2]$latch } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.585 ns" { clk clk~out0 c_st.red c_st~223 Selector6~138 Selector6~139 output[2]$latch } { 0.000ns 0.000ns 1.553ns 0.398ns 0.498ns 0.327ns 3.659ns } { 0.000ns 0.828ns 0.698ns 0.075ns 0.183ns 0.183ns 0.183ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.923 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns c_st.green 2 REG LC_X17_Y30_N0 4 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N0; Fanout = 4; REG Node = 'c_st.green'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { clk c_st.green } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.green } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.green } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.585 ns" { clk c_st.red c_st~223 Selector6~138 Selector6~139 output[2]$latch } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.585 ns" { clk clk~out0 c_st.red c_st~223 Selector6~138 Selector6~139 output[2]$latch } { 0.000ns 0.000ns 1.553ns 0.398ns 0.498ns 0.327ns 3.659ns } { 0.000ns 0.828ns 0.698ns 0.075ns 0.183ns 0.183ns 0.183ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.green } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.green } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.687 ns - Shortest register register " "Info: - Shortest register to register delay is 0.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c_st.green 1 REG LC_X17_Y30_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N0; Fanout = 4; REG Node = 'c_st.green'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_st.green } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.280 ns) 0.687 ns output\[2\]\$latch 2 REG LC_X17_Y30_N4 1 " "Info: 2: + IC(0.407 ns) + CELL(0.280 ns) = 0.687 ns; Loc. = LC_X17_Y30_N4; Fanout = 1; REG Node = 'output\[2\]\$latch'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.687 ns" { c_st.green output[2]$latch } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 40.76 % ) " "Info: Total cell delay = 0.280 ns ( 40.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.407 ns ( 59.24 % ) " "Info: Total interconnect delay = 0.407 ns ( 59.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.687 ns" { c_st.green output[2]$latch } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.687 ns" { c_st.green output[2]$latch } { 0.000ns 0.407ns } { 0.000ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.585 ns" { clk c_st.red c_st~223 Selector6~138 Selector6~139 output[2]$latch } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.585 ns" { clk clk~out0 c_st.red c_st~223 Selector6~138 Selector6~139 output[2]$latch } { 0.000ns 0.000ns 1.553ns 0.398ns 0.498ns 0.327ns 3.659ns } { 0.000ns 0.828ns 0.698ns 0.075ns 0.183ns 0.183ns 0.183ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.green } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.green } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.687 ns" { c_st.green output[2]$latch } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.687 ns" { c_st.green output[2]$latch } { 0.000ns 0.407ns } { 0.000ns 0.280ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "c_st.red time\[2\] clk 3.011 ns register " "Info: tsu for register \"c_st.red\" (data pin = \"time\[2\]\", clock pin = \"clk\") is 3.011 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.924 ns + Longest pin register " "Info: + Longest pin to register delay is 5.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns time\[2\] 1 CLK PIN_C15 6 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C15; Fanout = 6; CLK Node = 'time\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { time[2] } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.937 ns) + CELL(0.183 ns) 5.207 ns c_st~227 2 COMB LC_X18_Y30_N2 1 " "Info: 2: + IC(3.937 ns) + CELL(0.183 ns) = 5.207 ns; Loc. = LC_X18_Y30_N2; Fanout = 1; COMB Node = 'c_st~227'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.120 ns" { time[2] c_st~227 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.223 ns) 5.924 ns c_st.red 3 REG LC_X17_Y30_N8 5 " "Info: 3: + IC(0.494 ns) + CELL(0.223 ns) = 5.924 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.717 ns" { c_st~227 c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns ( 25.20 % ) " "Info: Total cell delay = 1.493 ns ( 25.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.431 ns ( 74.80 % ) " "Info: Total interconnect delay = 4.431 ns ( 74.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.924 ns" { time[2] c_st~227 c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.924 ns" { time[2] time[2]~out0 c_st~227 c_st.red } { 0.000ns 0.000ns 3.937ns 0.494ns } { 0.000ns 1.087ns 0.183ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.923 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns c_st.red 2 REG LC_X17_Y30_N8 5 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { clk c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.924 ns" { time[2] c_st~227 c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.924 ns" { time[2] time[2]~out0 c_st~227 c_st.red } { 0.000ns 0.000ns 3.937ns 0.494ns } { 0.000ns 1.087ns 0.183ns 0.223ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk output\[1\] output\[1\]\$latch 12.944 ns register " "Info: tco from clock \"clk\" to destination pin \"output\[1\]\" through register \"output\[1\]\$latch\" is 12.944 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.479 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.698 ns) 3.079 ns c_st.red 2 REG LC_X17_Y30_N8 5 " "Info: 2: + IC(1.553 ns) + CELL(0.698 ns) = 3.079 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.251 ns" { clk c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.075 ns) 3.552 ns c_st~223 3 COMB LC_X17_Y30_N9 2 " "Info: 3: + IC(0.398 ns) + CELL(0.075 ns) = 3.552 ns; Loc. = LC_X17_Y30_N9; Fanout = 2; COMB Node = 'c_st~223'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.473 ns" { c_st.red c_st~223 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.183 ns) 4.233 ns Selector6~138 4 COMB LC_X18_Y30_N3 1 " "Info: 4: + IC(0.498 ns) + CELL(0.183 ns) = 4.233 ns; Loc. = LC_X18_Y30_N3; Fanout = 1; COMB Node = 'Selector6~138'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.681 ns" { c_st~223 Selector6~138 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.183 ns) 4.743 ns Selector6~139 5 COMB LC_X18_Y30_N6 3 " "Info: 5: + IC(0.327 ns) + CELL(0.183 ns) = 4.743 ns; Loc. = LC_X18_Y30_N6; Fanout = 3; COMB Node = 'Selector6~139'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.510 ns" { Selector6~138 Selector6~139 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.661 ns) + CELL(0.075 ns) 8.479 ns output\[1\]\$latch 6 REG LC_X17_Y30_N2 1 " "Info: 6: + IC(3.661 ns) + CELL(0.075 ns) = 8.479 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'output\[1\]\$latch'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.736 ns" { Selector6~139 output[1]$latch } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.042 ns ( 24.08 % ) " "Info: Total cell delay = 2.042 ns ( 24.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.437 ns ( 75.92 % ) " "Info: Total interconnect delay = 6.437 ns ( 75.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.479 ns" { clk c_st.red c_st~223 Selector6~138 Selector6~139 output[1]$latch } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.479 ns" { clk clk~out0 c_st.red c_st~223 Selector6~138 Selector6~139 output[1]$latch } { 0.000ns 0.000ns 1.553ns 0.398ns 0.498ns 0.327ns 3.661ns } { 0.000ns 0.828ns 0.698ns 0.075ns 0.183ns 0.183ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.465 ns + Longest register pin " "Info: + Longest register to pin delay is 4.465 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns output\[1\]\$latch 1 REG LC_X17_Y30_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'output\[1\]\$latch'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { output[1]$latch } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.061 ns) + CELL(2.404 ns) 4.465 ns output\[1\] 2 PIN PIN_E14 0 " "Info: 2: + IC(2.061 ns) + CELL(2.404 ns) = 4.465 ns; Loc. = PIN_E14; Fanout = 0; PIN Node = 'output\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.465 ns" { output[1]$latch output[1] } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 53.84 % ) " "Info: Total cell delay = 2.404 ns ( 53.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns ( 46.16 % ) " "Info: Total interconnect delay = 2.061 ns ( 46.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.465 ns" { output[1]$latch output[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.465 ns" { output[1]$latch output[1] } { 0.000ns 2.061ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.479 ns" { clk c_st.red c_st~223 Selector6~138 Selector6~139 output[1]$latch } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.479 ns" { clk clk~out0 c_st.red c_st~223 Selector6~138 Selector6~139 output[1]$latch } { 0.000ns 0.000ns 1.553ns 0.398ns 0.498ns 0.327ns 3.661ns } { 0.000ns 0.828ns 0.698ns 0.075ns 0.183ns 0.183ns 0.075ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.465 ns" { output[1]$latch output[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.465 ns" { output[1]$latch output[1] } { 0.000ns 2.061ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "c_st.yellow time\[2\] clk 0.100 ns register " "Info: th for register \"c_st.yellow\" (data pin = \"time\[2\]\", clock pin = \"clk\") is 0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.923 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns c_st.yellow 2 REG LC_X17_Y30_N6 3 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N6; Fanout = 3; REG Node = 'c_st.yellow'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { clk c_st.yellow } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.yellow } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.yellow } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.923 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns time\[2\] 1 CLK PIN_C15 6 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C15; Fanout = 6; CLK Node = 'time\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { time[2] } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.280 ns) 2.566 ns c_st~224 2 COMB LC_X17_Y30_N5 2 " "Info: 2: + IC(1.199 ns) + CELL(0.280 ns) = 2.566 ns; Loc. = LC_X17_Y30_N5; Fanout = 2; COMB Node = 'c_st~224'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.479 ns" { time[2] c_st~224 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 2.923 ns c_st.yellow 3 REG LC_X17_Y30_N6 3 " "Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 2.923 ns; Loc. = LC_X17_Y30_N6; Fanout = 3; REG Node = 'c_st.yellow'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.357 ns" { c_st~224 c_st.yellow } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 54.40 % ) " "Info: Total cell delay = 1.590 ns ( 54.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.333 ns ( 45.60 % ) " "Info: Total interconnect delay = 1.333 ns ( 45.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { time[2] c_st~224 c_st.yellow } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { time[2] time[2]~out0 c_st~224 c_st.yellow } { 0.000ns 0.000ns 1.199ns 0.134ns } { 0.000ns 1.087ns 0.280ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.yellow } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.yellow } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { time[2] c_st~224 c_st.yellow } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { time[2] time[2]~out0 c_st~224 c_st.yellow } { 0.000ns 0.000ns 1.199ns 0.134ns } { 0.000ns 1.087ns 0.280ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}