vhdl10.tan.qmsg

来自「程序提供了一种简单高效的模拟交通灯控制器的算法」· QMSG 代码 · 共 14 行 · 第 1/4 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "time\[2\] " "Info: Assuming node \"time\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "time\[1\] " "Info: Assuming node \"time\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "time\[0\] " "Info: Assuming node \"time\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Selector6~139 " "Info: Detected gated clock \"Selector6~139\" as buffer" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 26 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector6~139" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector6~138 " "Info: Detected gated clock \"Selector6~138\" as buffer" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 26 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector6~138" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "c_st.green " "Info: Detected ripple clock \"c_st.green\" as buffer" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "c_st.green" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "c_st~223 " "Info: Detected gated clock \"c_st~223\" as buffer" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "c_st~223" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal2~26 " "Info: Detected gated clock \"Equal2~26\" as buffer" {  } { { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal2~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "c_st.red " "Info: Detected ripple clock \"c_st.red\" as buffer" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "c_st.red" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "c_st~224 " "Info: Detected gated clock \"c_st~224\" as buffer" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "c_st~224" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register c_st.red c_st.red 422.12 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 422.12 MHz between source register \"c_st.red\" and destination register \"c_st.red\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.347 ns + Longest register register " "Info: + Longest register to register delay is 1.347 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c_st.red 1 REG LC_X17_Y30_N8 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.075 ns) 0.630 ns c_st~227 2 COMB LC_X18_Y30_N2 1 " "Info: 2: + IC(0.555 ns) + CELL(0.075 ns) = 0.630 ns; Loc. = LC_X18_Y30_N2; Fanout = 1; COMB Node = 'c_st~227'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.630 ns" { c_st.red c_st~227 } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.223 ns) 1.347 ns c_st.red 3 REG LC_X17_Y30_N8 5 " "Info: 3: + IC(0.494 ns) + CELL(0.223 ns) = 1.347 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.717 ns" { c_st~227 c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.298 ns ( 22.12 % ) " "Info: Total cell delay = 0.298 ns ( 22.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.049 ns ( 77.88 % ) " "Info: Total interconnect delay = 1.049 ns ( 77.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.347 ns" { c_st.red c_st~227 c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.347 ns" { c_st.red c_st~227 c_st.red } { 0.000ns 0.555ns 0.494ns } { 0.000ns 0.075ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.923 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns c_st.red 2 REG LC_X17_Y30_N8 5 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { clk c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.923 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns c_st.red 2 REG LC_X17_Y30_N8 5 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X17_Y30_N8; Fanout = 5; REG Node = 'c_st.red'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { clk c_st.red } "NODE_NAME" } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.347 ns" { c_st.red c_st~227 c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.347 ns" { c_st.red c_st~227 c_st.red } { 0.000ns 0.555ns 0.494ns } { 0.000ns 0.075ns 0.223ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { clk c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { clk clk~out0 c_st.red } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_st.red } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { c_st.red } {  } {  } } } { "../Vhdl10.vhd" "" { Text "E:/new vhdl/Vhdl10.vhd" 17 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 3 " "Warning: Circuit may not operate. Detected 3 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}