📄 vhdl10.hier_info
字号:
|Vhdl10
clk => c_st~3.IN1
reset => c_st~0.OUTPUTSELECT
reset => c_st~1.OUTPUTSELECT
reset => c_st~2.OUTPUTSELECT
time[0] => Equal0.IN5
time[0] => Equal1.IN5
time[0] => Equal2.IN5
time[1] => Equal0.IN4
time[1] => Equal1.IN4
time[1] => Equal2.IN4
time[2] => Equal0.IN3
time[2] => Equal1.IN3
time[2] => Equal2.IN3
output[0] <= output[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
output[1] <= output[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
output[2] <= output[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
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