vhdl5.sim.qmsg

程序提供了一种简单高效的并入串出寄存器的算法

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 03 01:31:52 2008 " "Info: Processing started: Thu Jan 03 01:31:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off vhdl5 -c vhdl5 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off vhdl5 -c vhdl5" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|vhdl5\|REG8\[0\] " "Info: Register: \|vhdl5\|REG8\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Warning" "WEDS_GLITCH_DETECTED" "0.83 ns 0.83 ns \|vhdl5\|CLK " "Warning: Found glitch at time 0.83 ns of duration 0.83 ns on node \"\|vhdl5\|CLK\"" {  } {  } 0 0 "Found glitch at time %1!s! of duration %2!s! on node \"%3!s!\"" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     28.57 % " "Info: Simulation coverage is      28.57 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "204 " "Info: Number of transitions in simulation is 204" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "vhdl5.sim.vwf " "Info: Vector file vhdl5.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 1  Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 01:31:52 2008 " "Info: Processing ended: Thu Jan 03 01:31:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}