vhdl5.tan.qmsg

程序提供了一种简单高效的并入串出寄存器的算法

{ "Info" "ITDB_TSU_RESULT" "DATAOUT~reg0 LOAD CLK 2.346 ns register " "Info: tsu for register \"DATAOUT~reg0\" (data pin = \"LOAD\", clock pin = \"CLK\") is 2.346 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.334 ns + Longest pin register " "Info: + Longest pin to register delay is 5.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns LOAD 1 PIN PIN_N14 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N14; Fanout = 2; PIN Node = 'LOAD'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LOAD } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.708 ns) + CELL(0.539 ns) 5.334 ns DATAOUT~reg0 2 REG LC_X17_Y1_N4 2 " "Info: 2: + IC(3.708 ns) + CELL(0.539 ns) = 5.334 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.247 ns" { LOAD DATAOUT~reg0 } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 30.48 % ) " "Info: Total cell delay = 1.626 ns ( 30.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.708 ns ( 69.52 % ) " "Info: Total interconnect delay = 3.708 ns ( 69.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.334 ns" { LOAD DATAOUT~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.334 ns" { LOAD LOAD~out0 DATAOUT~reg0 } { 0.000ns 0.000ns 3.708ns } { 0.000ns 1.087ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.998 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.542 ns) 2.998 ns DATAOUT~reg0 2 REG LC_X17_Y1_N4 2 " "Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.170 ns" { CLK DATAOUT~reg0 } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.70 % ) " "Info: Total cell delay = 1.370 ns ( 45.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.628 ns ( 54.30 % ) " "Info: Total interconnect delay = 1.628 ns ( 54.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.998 ns" { CLK DATAOUT~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.998 ns" { CLK CLK~out0 DATAOUT~reg0 } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.334 ns" { LOAD DATAOUT~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.334 ns" { LOAD LOAD~out0 DATAOUT~reg0 } { 0.000ns 0.000ns 3.708ns } { 0.000ns 1.087ns 0.539ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.998 ns" { CLK DATAOUT~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.998 ns" { CLK CLK~out0 DATAOUT~reg0 } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DATAOUT DATAOUT~reg0 6.718 ns register " "Info: tco from clock \"CLK\" to destination pin \"DATAOUT\" through register \"DATAOUT~reg0\" is 6.718 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.998 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.542 ns) 2.998 ns DATAOUT~reg0 2 REG LC_X17_Y1_N4 2 " "Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.170 ns" { CLK DATAOUT~reg0 } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.70 % ) " "Info: Total cell delay = 1.370 ns ( 45.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.628 ns ( 54.30 % ) " "Info: Total interconnect delay = 1.628 ns ( 54.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.998 ns" { CLK DATAOUT~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.998 ns" { CLK CLK~out0 DATAOUT~reg0 } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.564 ns + Longest register pin " "Info: + Longest register to pin delay is 3.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATAOUT~reg0 1 REG LC_X17_Y1_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATAOUT~reg0 } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.160 ns) + CELL(2.404 ns) 3.564 ns DATAOUT 2 PIN PIN_W14 0 " "Info: 2: + IC(1.160 ns) + CELL(2.404 ns) = 3.564 ns; Loc. = PIN_W14; Fanout = 0; PIN Node = 'DATAOUT'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.564 ns" { DATAOUT~reg0 DATAOUT } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.45 % ) " "Info: Total cell delay = 2.404 ns ( 67.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.160 ns ( 32.55 % ) " "Info: Total interconnect delay = 1.160 ns ( 32.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.564 ns" { DATAOUT~reg0 DATAOUT } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.564 ns" { DATAOUT~reg0 DATAOUT } { 0.000ns 1.160ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.998 ns" { CLK DATAOUT~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.998 ns" { CLK CLK~out0 DATAOUT~reg0 } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.564 ns" { DATAOUT~reg0 DATAOUT } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.564 ns" { DATAOUT~reg0 DATAOUT } { 0.000ns 1.160ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "REG8\[0\] DATAIN\[7\] CLK -2.109 ns register " "Info: th for register \"REG8\[0\]\" (data pin = \"DATAIN\[7\]\", clock pin = \"CLK\") is -2.109 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.998 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.542 ns) 2.998 ns REG8\[0\] 2 REG LC_X17_Y1_N3 1 " "Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N3; Fanout = 1; REG Node = 'REG8\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.170 ns" { CLK REG8[0] } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.70 % ) " "Info: Total cell delay = 1.370 ns ( 45.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.628 ns ( 54.30 % ) " "Info: Total interconnect delay = 1.628 ns ( 54.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.998 ns" { CLK REG8[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.998 ns" { CLK CLK~out0 REG8[0] } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.207 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.207 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns DATAIN\[7\] 1 PIN PIN_U15 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U15; Fanout = 1; PIN Node = 'DATAIN\[7\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATAIN[7] } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.662 ns) + CELL(0.458 ns) 5.207 ns REG8\[0\] 2 REG LC_X17_Y1_N3 1 " "Info: 2: + IC(3.662 ns) + CELL(0.458 ns) = 5.207 ns; Loc. = LC_X17_Y1_N3; Fanout = 1; REG Node = 'REG8\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.120 ns" { DATAIN[7] REG8[0] } "NODE_NAME" } } { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.545 ns ( 29.67 % ) " "Info: Total cell delay = 1.545 ns ( 29.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.662 ns ( 70.33 % ) " "Info: Total interconnect delay = 3.662 ns ( 70.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.207 ns" { DATAIN[7] REG8[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.207 ns" { DATAIN[7] DATAIN[7]~out0 REG8[0] } { 0.000ns 0.000ns 3.662ns } { 0.000ns 1.087ns 0.458ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.998 ns" { CLK REG8[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.998 ns" { CLK CLK~out0 REG8[0] } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.207 ns" { DATAIN[7] REG8[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.207 ns" { DATAIN[7] DATAIN[7]~out0 REG8[0] } { 0.000ns 0.000ns 3.662ns } { 0.000ns 1.087ns 0.458ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 01:29:53 2008 " "Info: Processing ended: Thu Jan 03 01:29:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}