vhdl5.vhd

来自「程序提供了一种简单高效的并入串出寄存器的算法」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vhdl5 IS
    PORT (CLK,LOAD:IN STD_LOGIC;
            DATAIN:IN STD_LOGIC_VECTOR ( 7 DOWNTO 0);
           DATAOUT:OUT STD_LOGIC );
END vhdl5;
ARCHITECTURE BEHAV OF vhdl5 IS

SIGNAL REG8 : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ):="11111111";
BEGIN
PROCESS (CLK,LOAD,REG8)
BEGIN

    
      IF LOAD = '1' THEN
       REG8 <= DATAIN;
        ELSE FOR n IN 0 TO 7 LOOP
        IF CLK'EVENT AND CLK = '1' THEN
        REG8 ( 7 DOWNTO 1 ) <= REG8 ( 6 DOWNTO 0 );
        
        REG8(0) <= DATAIN(n);
        DATAOUT <= REG8(0); 
        
        END IF;
        END LOOP; 
    END IF;
  
END PROCESS;
END BEHAV;