vhdl5.tan.rpt

程序提供了一种简单高效的并入串出寄存器的算法

+-------+--------------+------------+-----------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From      ; To           ; To Clock ;
+-------+--------------+------------+-----------+--------------+----------+
; N/A   ; None         ; 2.346 ns   ; LOAD      ; DATAOUT~reg0 ; CLK      ;
; N/A   ; None         ; 2.219 ns   ; DATAIN[7] ; REG8[0]      ; CLK      ;
+-------+--------------+------------+-----------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.718 ns   ; DATAOUT~reg0 ; DATAOUT ; CLK        ;
+-------+--------------+------------+--------------+---------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+-----------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To           ; To Clock ;
+---------------+-------------+-----------+-----------+--------------+----------+
; N/A           ; None        ; -2.109 ns ; DATAIN[7] ; REG8[0]      ; CLK      ;
; N/A           ; None        ; -2.236 ns ; LOAD      ; DATAOUT~reg0 ; CLK      ;
+---------------+-------------+-----------+-----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 03 01:29:53 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vhdl5 -c vhdl5 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 422.12 MHz between source register "REG8[0]" and destination register "DATAOUT~reg0"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.717 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y1_N3; Fanout = 1; REG Node = 'REG8[0]'
            Info: 2: + IC(0.398 ns) + CELL(0.319 ns) = 0.717 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'
            Info: Total cell delay = 0.319 ns ( 44.49 % )
            Info: Total interconnect delay = 0.398 ns ( 55.51 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.998 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'
                Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'
                Info: Total cell delay = 1.370 ns ( 45.70 % )
                Info: Total interconnect delay = 1.628 ns ( 54.30 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.998 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'
                Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N3; Fanout = 1; REG Node = 'REG8[0]'
                Info: Total cell delay = 1.370 ns ( 45.70 % )
                Info: Total interconnect delay = 1.628 ns ( 54.30 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "DATAOUT~reg0" (data pin = "LOAD", clock pin = "CLK") is 2.346 ns
    Info: + Longest pin to register delay is 5.334 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N14; Fanout = 2; PIN Node = 'LOAD'
        Info: 2: + IC(3.708 ns) + CELL(0.539 ns) = 5.334 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'
        Info: Total cell delay = 1.626 ns ( 30.48 % )
        Info: Total interconnect delay = 3.708 ns ( 69.52 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.998 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'
        Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'
        Info: Total cell delay = 1.370 ns ( 45.70 % )
        Info: Total interconnect delay = 1.628 ns ( 54.30 % )
Info: tco from clock "CLK" to destination pin "DATAOUT" through register "DATAOUT~reg0" is 6.718 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.998 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'
        Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'
        Info: Total cell delay = 1.370 ns ( 45.70 % )
        Info: Total interconnect delay = 1.628 ns ( 54.30 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.564 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y1_N4; Fanout = 2; REG Node = 'DATAOUT~reg0'
        Info: 2: + IC(1.160 ns) + CELL(2.404 ns) = 3.564 ns; Loc. = PIN_W14; Fanout = 0; PIN Node = 'DATAOUT'
        Info: Total cell delay = 2.404 ns ( 67.45 % )
        Info: Total interconnect delay = 1.160 ns ( 32.55 % )
Info: th for register "REG8[0]" (data pin = "DATAIN[7]", clock pin = "CLK") is -2.109 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.998 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'CLK'
        Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X17_Y1_N3; Fanout = 1; REG Node = 'REG8[0]'
        Info: Total cell delay = 1.370 ns ( 45.70 % )
        Info: Total interconnect delay = 1.628 ns ( 54.30 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.207 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U15; Fanout = 1; PIN Node = 'DATAIN[7]'
        Info: 2: + IC(3.662 ns) + CELL(0.458 ns) = 5.207 ns; Loc. = LC_X17_Y1_N3; Fanout = 1; REG Node = 'REG8[0]'
        Info: Total cell delay = 1.545 ns ( 29.67 % )
        Info: Total interconnect delay = 3.662 ns ( 70.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jan 03 01:29:53 2008
    Info: Elapsed time: 00:00:00