vhdl2.hier_info

程序提供了一种高效简单的38译码器的算法

|Vhdl2
d[0] => Mux0.IN10
d[0] => Mux1.IN10
d[0] => Mux2.IN10
d[0] => Mux3.IN10
d[0] => Mux4.IN10
d[0] => Mux5.IN10
d[0] => Mux6.IN10
d[0] => Mux7.IN10
d[1] => Mux0.IN9
d[1] => Mux1.IN9
d[1] => Mux2.IN9
d[1] => Mux3.IN9
d[1] => Mux4.IN9
d[1] => Mux5.IN9
d[1] => Mux6.IN9
d[1] => Mux7.IN9
d[2] => Mux0.IN8
d[2] => Mux1.IN8
d[2] => Mux2.IN8
d[2] => Mux3.IN8
d[2] => Mux4.IN8
d[2] => Mux5.IN8
d[2] => Mux6.IN8
d[2] => Mux7.IN8
G1 => process0~0.IN1
G2A => process0~0.IN0
G2B => process0~1.IN1
y[0] <= y~7.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= y~6.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= y~5.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= y~4.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= y~3.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= y~2.DB_MAX_OUTPUT_PORT_TYPE
y[6] <= y~1.DB_MAX_OUTPUT_PORT_TYPE
y[7] <= y~0.DB_MAX_OUTPUT_PORT_TYPE