vhdl1.tan.qmsg

程序提供了一种2选1选择器的算法

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 29 00:28:08 2007 " "Info: Processing started: Sat Dec 29 00:28:08 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Vhdl1 -c Vhdl1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Vhdl1 -c Vhdl1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "s c 8.461 ns Longest " "Info: Longest tpd from source pin \"s\" to destination pin \"c\" is 8.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns s 1 PIN PIN_Y3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y3; Fanout = 1; PIN Node = 's'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { s } "NODE_NAME" } } { "Vhdl1.vhd" "" { Text "E:/new vhdl/Vhdl1/Vhdl1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.673 ns) + CELL(0.183 ns) 4.943 ns c~8 2 COMB LC_X52_Y1_N2 1 " "Info: 2: + IC(3.673 ns) + CELL(0.183 ns) = 4.943 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; COMB Node = 'c~8'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.856 ns" { s c~8 } "NODE_NAME" } } { "Vhdl1.vhd" "" { Text "E:/new vhdl/Vhdl1/Vhdl1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(2.404 ns) 8.461 ns c 3 PIN PIN_AA3 0 " "Info: 3: + IC(1.114 ns) + CELL(2.404 ns) = 8.461 ns; Loc. = PIN_AA3; Fanout = 0; PIN Node = 'c'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.518 ns" { c~8 c } "NODE_NAME" } } { "Vhdl1.vhd" "" { Text "E:/new vhdl/Vhdl1/Vhdl1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.674 ns ( 43.42 % ) " "Info: Total cell delay = 3.674 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.787 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.787 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.461 ns" { s c~8 c } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.461 ns" { s s~out0 c~8 c } { 0.000ns 0.000ns 3.673ns 1.114ns } { 0.000ns 1.087ns 0.183ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 29 00:28:08 2007 " "Info: Processing ended: Sat Dec 29 00:28:08 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}