risc1.cr.mti

RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数

E:/summer_intern/code/7_15/3/RSIC_SPM.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/RSIC_SPM.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module RISC_SPM

Top level modules:
	RISC_SPM

} {} {}} E:/summer_intern/code/7_15/3/Memory_Unit.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Memory_Unit.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Memory_Unit

Top level modules:
	Memory_Unit

} {} {}} E:/summer_intern/code/7_15/3/Multiplexer_3ch.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Multiplexer_3ch.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Multiplexer_3ch

Top level modules:
	Multiplexer_3ch

} {} {}} E:/summer_intern/code/7_15/3/Multiplexer_5ch.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Multiplexer_5ch.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Multiplexer_5ch

Top level modules:
	Multiplexer_5ch

} {} {}} E:/summer_intern/code/7_15/3/Register_Unit.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Register_Unit.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Register_Unit

Top level modules:
	Register_Unit

} {} {}} E:/summer_intern/code/7_15/3/test_RISC_SPM.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/test_RISC_SPM.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module test_RISC_SPM

Top level modules:
	test_RISC_SPM

} {} {}} E:/summer_intern/code/7_15/3/Control_Unit.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Control_Unit.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Control_Unit

Top level modules:
	Control_Unit

} {} {}} E:/summer_intern/code/7_15/3/Address_Register.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Address_Register.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Address_Register

Top level modules:
	Address_Register

} {} {}} E:/summer_intern/code/7_15/3/Alu_RISC.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Alu_RISC.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Alu_RISC

Top level modules:
	Alu_RISC

} {} {}} {E:/summer_intern/code/7_15/3/Clock_Unit .v} {1 {vlog -work work -vopt -nocovercells {E:/summer_intern/code/7_15/3/Clock_Unit .v}
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Clock_Unit

Top level modules:
	Clock_Unit

} {} {}} E:/summer_intern/code/7_15/3/D_flop.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/D_flop.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module D_flop

Top level modules:
	D_flop

} {} {}} E:/summer_intern/code/7_15/3/Processing_Unit.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Processing_Unit.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Processing_Unit

Top level modules:
	Processing_Unit

} {} {}} E:/summer_intern/code/7_15/3/Instruction_Register.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Instruction_Register.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Instruction_Register

Top level modules:
	Instruction_Register

} {} {}} E:/summer_intern/code/7_15/3/Program_Counter.v {1 {vlog -work work -vopt -nocovercells E:/summer_intern/code/7_15/3/Program_Counter.v
Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
-- Compiling module Program_Counter

Top level modules:
	Program_Counter

} {} {}}