alu_risc.v

来自「RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优」· Verilog 代码 · 共 24 行

module Alu_RISC (alu_zero_flag, alu_out, data_1, data_2, sel);
  parameter word_size = 16, op_size = 12;
  // Opcodes
  parameter NOP = 12'b0000, ADD = 12'b0001, SUB = 12'b0010, AND = 12'b0011, 
    NOT = 12'b0100, RD = 12'b0101, WR = 12'b0110, BR	= 12'b0111, BRZ = 12'b1000;
  output 		alu_zero_flag;
  output [word_size-1: 0] 	alu_out;
  input 	[word_size-1: 0] 	data_1, data_2;
  input 	[op_size-1: 0] 	sel;
  reg 	 		[word_size-1: 0]alu_out_temp;
  assign alu_out=alu_out_temp;
  
  assign  alu_zero_flag = ~|alu_out_temp;
  always @ (sel or data_1 or data_2)  
     case  (sel)
      NOP:	alu_out_temp = 0;
      ADD:	alu_out_temp = data_1 + data_2; 
	 SUB:		alu_out_temp = data_2 - data_1;
      AND:	alu_out_temp = data_1 & data_2;
      NOT:	alu_out_temp = ~ data_2;	
      default: 	alu_out_temp = 0;
    endcase 
endmodule