program_counter.v

来自「RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优」· Verilog 代码 · 共 14 行

module Program_Counter (count, data_in, Load_PC, Inc_PC, clk, rst);
  parameter word_size = 16;
  output [word_size-1: 0] 	count;
  input 	[word_size-1: 0] 	data_in;
  input 			Load_PC, Inc_PC;
  input 			clk, rst;
  reg 			[word_size-1: 0]count_temp; 
  assign count=count_temp;
  always @ (posedge clk or negedge rst)
  	if (rst == 0) count_temp <= 0; 
    	else if (Load_PC) count_temp <= data_in; 
    	else if  (Inc_PC) count_temp <= count_temp +1;
endmodule