test_risc_spm.v.bak

RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数

module test_RISC_SPM ();
  reg rst;
  wire clk;
  parameter word_size = 16;
  reg [8: 0] k;
  Clock_Unit M1 (clk);
  RISC_SPM M2 (clk, rst);
// define probes
  wire [word_size-1: 0] word0, word1, word2, word3,word4, word5,word6, 
  word7,word8, word9,word10, word11,word12, word13, word14;		// instructions
  wire [word_size-1: 0] word128, word129,word130, word131,word132,
   word133,word134, word135,word136, word137,word138, word139, word140;	// data
  assign word0 = M2.M2_SRAM.memory[0];  	// words 1 to 13 
  assign word1 = M2.M2_SRAM.memory[1];
  assign word2 = M2.M2_SRAM.memory[2];
  assign word3 = M2.M2_SRAM.memory[3];
  assign word4 = M2.M2_SRAM.memory[4];
  assign word5 = M2.M2_SRAM.memory[5];
  assign word6 = M2.M2_SRAM.memory[6];
  assign word7 = M2.M2_SRAM.memory[7];
  assign word8 = M2.M2_SRAM.memory[8];
  assign word9 = M2.M2_SRAM.memory[9];
  assign word10 = M2.M2_SRAM.memory[10];
  assign word11 = M2.M2_SRAM.memory[11];
  assign word12 = M2.M2_SRAM.memory[12];
  assign word13 = M2.M2_SRAM.memory[13];
  assign word14 = M2.M2_SRAM.memory[14]; 
  
  assign word128 = M2.M2_SRAM.memory[128];
  assign word129 = M2.M2_SRAM.memory[129];
  assign word130 = M2.M2_SRAM.memory[130];
  assign word131 = M2.M2_SRAM.memory[131];
  assign word132 = M2.M2_SRAM.memory[132];
  assign word133 = M2.M2_SRAM.memory[133];
  assign word134 = M2.M2_SRAM.memory[134];
  assign word135 = M2.M2_SRAM.memory[135];
  assign word136 = M2.M2_SRAM.memory[136];
  assign word137 = M2.M2_SRAM.memory[137];
  assign word138 = M2.M2_SRAM.memory[138];
  assign word139 = M2.M2_SRAM.memory[139];  	// words 129 to 139 
  assign word140 = M2.M2_SRAM.memory[140]; 
   initial #2800 $finish;		// set end point for simulation
 initial begin: Flush_Memory
  #2 rst = 0; for (k=0; k<=255; k=k+1) M2.M2_SRAM.memory[k] = 0; #10 rst = 1;  end // Flush_Memory
initial begin: Load_program #5
			 	 // opcode_src_dest
  M2.M2_SRAM.memory[0] = 16'b00000000_0000_00_00;	// NOP
  M2.M2_SRAM.memory[1] = 16'b00000000_0101_00_10;	// Read Mem[130] to R2
  M2.M2_SRAM.memory[2] = 130;			// R2 = 2
  M2.M2_SRAM.memory[3] = 16'b00000000_0101_00_11;	// Read Mem[131] to R3
  M2.M2_SRAM.memory[4] = 131;			// R3 = 0
  M2.M2_SRAM.memory[5] = 16'b00000000_0101_00_01;	// Read Mem[128] to R1
  M2.M2_SRAM.memory[6] = 128;			// R1 = 6
  M2.M2_SRAM.memory[7] = 16'b00000000_0101_00_00;	// Read Mem[129] to R0
  M2.M2_SRAM.memory[8] = 129;			// R0 = 1
  M2.M2_SRAM.memory[9]   = 16'b00000000_0010_00_01;	// Sub R1-R0 to R1
  M2.M2_SRAM.memory[10] = 16'b00000000_1000_00_00;	// BRZ 
  M2.M2_SRAM.memory[11] = 134;		         // Holds address for BRZ  (139)
  M2.M2_SRAM.memory[12] = 16'b00000000_0001_10_11;	// Add R2+R3 to R3
  M2.M2_SRAM.memory[13] = 16'b00000000_0111_00_11;	// BR
  M2.M2_SRAM.memory[14] = 140;		         // Holds address for BR  (9)
  // Load data
  M2.M2_SRAM.memory[128] = 6; M2.M2_SRAM.memory[129] = 1;
  M2.M2_SRAM.memory[130] = 2; M2.M2_SRAM.memory[131] = 0;
  M2.M2_SRAM.memory[134] = 139; M2.M2_SRAM.memory[135] = 0;
  M2.M2_SRAM.memory[139] = 16'b00000000_1111_00_00;	// HALT
  M2.M2_SRAM.memory[140] = 9;			//  Repeat Loop
end 
endmodule