d_flop.v

来自「RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优」· Verilog 代码 · 共 11 行

module D_flop (data_out, data_in, load, clk, rst);
  output 		data_out;
  input 		data_in;
  input 		load;
  input 		clk, rst;
  reg 		data_out;

  always @ (posedge clk or negedge rst)
    if (rst == 0) data_out <= 0; else if (load == 1)data_out <= data_in;
endmodule