_primary.vhd

来自「RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优」· VHDL 代码 · 共 58 行

library verilog;
use verilog.vl_types.all;
entity Control_Unit is
    generic(
        word_size       : integer := 16;
        op_size         : integer := 12;
        state_size      : integer := 4;
        src_size        : integer := 2;
        dest_size       : integer := 2;
        Sel1_size       : integer := 3;
        Sel2_size       : integer := 2;
        S_idle          : integer := 0;
        S_fet1          : integer := 1;
        S_fet2          : integer := 2;
        S_dec           : integer := 3;
        S_ex1           : integer := 4;
        S_rd1           : integer := 5;
        S_rd2           : integer := 6;
        S_wr1           : integer := 7;
        S_wr2           : integer := 8;
        S_br1           : integer := 9;
        S_br2           : integer := 10;
        S_halt          : integer := 11;
        NOP             : integer := 0;
        ADD             : integer := 1;
        SUB             : integer := 2;
        \AND\           : integer := 3;
        \NOT\           : integer := 4;
        RD              : integer := 5;
        WR              : integer := 6;
        BR              : integer := 7;
        BRZ             : integer := 8;
        R0              : integer := 0;
        R1              : integer := 1;
        R2              : integer := 2;
        R3              : integer := 3
    );
    port(
        Load_R0         : out    vl_logic;
        Load_R1         : out    vl_logic;
        Load_R2         : out    vl_logic;
        Load_R3         : out    vl_logic;
        Load_PC         : out    vl_logic;
        Inc_PC          : out    vl_logic;
        Sel_Bus_1_Mux   : out    vl_logic_vector;
        Sel_Bus_2_Mux   : out    vl_logic_vector;
        Load_IR         : out    vl_logic;
        Load_Add_R      : out    vl_logic;
        Load_Reg_Y      : out    vl_logic;
        Load_Reg_Z      : out    vl_logic;
        write           : out    vl_logic;
        instruction     : in     vl_logic_vector;
        zero            : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end Control_Unit;