_info

RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数

m255
K3
13
cModel Technology
dE:\summer_intern\code\7_15\2
vAddress_Register
VGc5l:lM4dCXi]k_1FUg^R3
r1
31
Ic^^B1Na<amh?BgMjaggC]0
Z0 dE:\summer_intern\code\7_15\3
w1216127939
8E:/summer_intern/code/7_15/3/Address_Register.v
FE:/summer_intern/code/7_15/3/Address_Register.v
L0 2
Z1 OE;L;6.3c;37
Z2 o-work work -nocovercells -L mtiAvm
n@address_@register
!s85 0
vAlu_RISC
V7]jZNN>U=C<[>VX<RLVJK2
r1
31
IgA99]P4YLYoBN1;9L:?1_0
Z3 dE:\summer_intern\code\7_15\3
w1216128005
8E:/summer_intern/code/7_15/3/Alu_RISC.v
FE:/summer_intern/code/7_15/3/Alu_RISC.v
L0 1
R1
R2
n@alu_@r@i@s@c
!s85 0
vClock_Unit
Va5oEK:`4V]cPZnj];Q`QR2
r1
31
I@YeeQS<g@Hk8kU23K13iS0
R3
w1208164880
8E:/summer_intern/code/7_15/3/Clock_Unit .v
FE:/summer_intern/code/7_15/3/Clock_Unit .v
L0 2
R1
R2
n@clock_@unit
!s85 0
vControl_Unit
VnHT8FIeQRNZNYOY<ZD[<i1
r1
31
I0k>^GVFaBKHUBcNQ5Kb<A2
R3
w1216193696
8E:/summer_intern/code/7_15/3/Control_Unit.v
FE:/summer_intern/code/7_15/3/Control_Unit.v
L0 1
R1
R2
n@control_@unit
!s85 0
vD_flop
V=BJEg<9IggeAkP5No=9Z;1
r1
31
I]90BTC[LfHlYNhZ3;UJ9a1
R3
w1208164652
8E:/summer_intern/code/7_15/3/D_flop.v
FE:/summer_intern/code/7_15/3/D_flop.v
L0 1
R1
R2
n@d_flop
!s85 0
vInstruction_Register
V0JcN:Y5RSln7fF2g1<I5O3
r1
31
IZYKFIPGG<ofC:nJKAEnV@1
R3
w1216194571
8E:/summer_intern/code/7_15/3/Instruction_Register.v
FE:/summer_intern/code/7_15/3/Instruction_Register.v
L0 2
R1
R2
n@instruction_@register
!s85 0
vMemory_Unit
VVNKe>CdBaC?GU8zo9dGig2
r1
!s85 0
31
Ia[@0Pa;I2<5ezNH3BH9m<2
R3
w1216127717
8E:/summer_intern/code/7_15/3/Memory_Unit.v
FE:/summer_intern/code/7_15/3/Memory_Unit.v
L0 2
R1
R2
n@memory_@unit
vMultiplexer_3ch
V__b>?^]`c7`6;`zMcZEDW0
r1
31
I6gdA=0]R@^QY`T9NKhMf61
R3
w1216127725
8E:/summer_intern/code/7_15/3/Multiplexer_3ch.v
FE:/summer_intern/code/7_15/3/Multiplexer_3ch.v
L0 2
R1
R2
n@multiplexer_3ch
!s85 0
vMultiplexer_5ch
Vj162oHkfGjaiiJY^eQ^[I2
r1
31
Ij_G@<?kAIHHkiP5c:H1^B3
R3
w1216194264
8E:/summer_intern/code/7_15/3/Multiplexer_5ch.v
FE:/summer_intern/code/7_15/3/Multiplexer_5ch.v
L0 1
R1
R2
n@multiplexer_5ch
!s85 0
vProcessing_Unit
V4N9:Q52?EJaO2MdLDe0CC1
r1
31
IknXOa^2;GiQ9fOQ^`VNEM1
R3
w1216194451
8E:/summer_intern/code/7_15/3/Processing_Unit.v
FE:/summer_intern/code/7_15/3/Processing_Unit.v
L0 1
R1
R2
n@processing_@unit
!s85 0
vProgram_Counter
VKkgRXK9Pzm4k@5>J5MQg=2
r1
31
I1:9YQ2AggK:6`NW]J_EAZ3
R3
w1216128064
8E:/summer_intern/code/7_15/3/Program_Counter.v
FE:/summer_intern/code/7_15/3/Program_Counter.v
L0 1
R1
R2
n@program_@counter
!s85 0
vRegister_Unit
VTPzN5c6geh^hI;a9YJa=K1
r1
31
InB_]ZAgZ663Q5K@agEHWB2
R3
w1216127745
8E:/summer_intern/code/7_15/3/Register_Unit.v
FE:/summer_intern/code/7_15/3/Register_Unit.v
L0 1
R1
R2
n@register_@unit
!s85 0
vRISC_SPM
VdIf>1i@2>ZnL`AJVZFz7n2
r1
31
IaoHGdY7Z1c86AP<mQ41413
R3
w1216127698
8E:/summer_intern/code/7_15/3/RSIC_SPM.v
FE:/summer_intern/code/7_15/3/RSIC_SPM.v
L0 2
R1
R2
n@r@i@s@c_@s@p@m
!s85 0
vtest_RISC_SPM
VoDL0V94nUKkcfM<OJnK1c3
r1
31
IS4?bGbj:ED_8PzH8Uz`Gl3
R3
w1216128924
8E:/summer_intern/code/7_15/3/test_RISC_SPM.v
FE:/summer_intern/code/7_15/3/test_RISC_SPM.v
L0 2
R1
R2
ntest_@r@i@s@c_@s@p@m
!s85 0