49_test.vhd

来自「VHDL语言100例详解」· VHDL 代码 · 共 22 行

entity delta is
end entity;

architecture archi_delta of delta is
	signal a : integer:=40;
	signal b : integer:=30;

begin
	process
	begin
		a <= b;
		b <= a;
		wait for 10 ns;
		a <= 40;
		b <= 30;
		wait for 20 ns;
		assert false 
		report "End of simulation"
		severity error;
	end process;
end;