36_gcd.vhd

来自「VHDL语言100例详解」· VHDL 代码 · 共 34 行

entity gcd is
port(start: in bit;
	 clk  : in bit;
	 din  : in bit;
	 xi,yi: in integer;
	 dout : out bit;
	 output:out integer);
end gcd;

architecture behavior of gcd is
begin
  process
	variable x,y:integer;
	begin
	  wait until((start='1')and(clk='1'and clk'event));
	  calculation:loop
	  wait until((din='1')and(clk='1'and clk'event));
	  dout<='0';
	  x:=xi;
	  y:=yi;
	  while(x/=y)loop
	  if(x<y)
		  then y:=y-x;
		  else x:=x-y;
      end if;
    end loop;
	wait until((din='0')and(clk='1' and clk'event));
	dout<='1';
	output<=x;
   end loop;
  end process;
end behavior;