46_default_generic.vhd

VHDL语言100例详解

library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_BAND is 
-----------------------------------------------------------
    generic(
		   lDelay : time);
	port(
		I  	: in std_logic;
		B 	: in std_logic;
		FOUT: out std_logic
		);
end B_BAND;

architecture FUNC of B_BAND is
begin
		FOUT <= (I and (not B))after lDelay;
end FUNC;

library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_AND2 is 
-----------------------------------------------------------
	generic
		(
		lDelay : time 
		);
	port(
		I0 	: in std_logic;
		I1  : in std_logic;
		FOUT: out std_logic
		);
end B_AND2;

architecture FUNC of B_AND2 is
begin
    FOUT <= I0 and I1 after lDelay;
end FUNC;

library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_OR2 is 
-----------------------------------------------------------
	generic
		(
		lDelay : time 
		);
	port(
		I0 	: in std_logic;
		I1  : in std_logic;
		FOUT: out std_logic
		);
end B_OR2;

architecture FUNC of B_OR2 is
begin
		FOUT <= (I0 or I1) after lDelay;
end FUNC;


library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_MUX2 is
-----------------------------------------------------------
   port(A      : in std_logic;
		B      : in std_logic;
		S0     : in std_logic;
		O      : out std_logic);
end B_MUX2;

architecture STRUC of B_MUX2 is
component B_AND2
	 generic(lDelay  : time:= 5 ns);
	 port(I0    : in std_logic;
		  I1    : in std_logic;
		  FOUT  : out std_logic);
end component;
component B_OR2
	generic(lDelay  : time:= 5 ns);
	port(I0    : in std_logic;
		 I1    : in std_logic;
	     FOUT  : out std_logic);
end component;
component B_BAND
	 generic(lDelay  : time:= 5 ns);
	 port(I     : in std_logic;
		  B     : in std_logic;
		  FOUT  : out std_logic);
end component;

for U0:B_BAND use entity work.B_BAND(FUNC);
for U1:B_AND2 use entity work.B_AND2(FUNC);
for U2:B_OR2 use entity work.B_OR2(FUNC);

signal sig1,sig2:   std_logic;

begin
U0: B_BAND
	port map(A,S0,sig1);
U1: B_AND2
	port map(S0,B,sig2);
U2: B_OR2
	port map(sig1,sig2,O);
end STRUC;