38_test_28.vhd

VHDL语言100例详解

--Page          :294,295

--Objective     :Multiple array inputs

--Filename      :test_28.vhd

--Author        :Joseph Pick

entity Test_28 is
end Test_28 ;

architecture Behave_1 of Test_28 is

  type Logic4 is ('x','0','1','z');
  type Logic4_Vector is array (NATURAL range <>) of Logic4;
  type Logic4_Table is array (Logic4,Logic4) of Logic4;

  constant Or_Table : Logic4_Table := (('x', 'x', '1', 'x'),
						   ('x', '0', '1', 'z'),
						   ('1', '1', '1', '1'),
						   ('x', 'z', '1', 'z'));
  
  function "or" (L_V,R_V : Logic4_Vector)
				return Logic4_Vector is
    variable Result : Logic4_Vector(1 to L_V'LENGTH);
  begin
	assert L_V'LENGTH = R_V'LENGTH
	   report "Length misatch of inputs"
	   severity ERROR;
    for I in Result'RANGE loop
	   Result(I) :=Or_Table(L_V(I-Result'Low+L_V'Low),R_V(I-Result'Low+R_V'Low));
    end loop;
	return Result;
  end "or";

begin

  Or_Range_Test:
  process
	variable Vector_0_8   : Logic4_Vector(0 to 8);
	variable Vector_3_11  : Logic4_Vector(3 to 11);
	variable Vector_15_23 : Logic4_Vector(15 to 23);
  begin
	Vector_0_8  :="000011101";
	Vector_3_11 :="111100000";
	Vector_15_23(15 to 23) := Vector_0_8(0 to 8) or 
							  Vector_3_11(3 to 11);
	wait for 50 ns;
  end process Or_Range_Test;
  proc_end:
  process
  begin
	wait for 100 ns;
	assert false
	   report "end"
	   severity ERROR;
	
  end process proc_end;
end Behave_1;