35_ram_controller.vhd

VHDL语言100例详解

library ieee;
use ieee.std_logic_1164.all;

entity  memory_control is
   port (
          clk,w_rb,ads_b,cs1 : in bit;
          rdy_b,we_b,cs_b : out bit := '1');
end memory_control;

architecture  behavel of memory_control is
  constant delay : time := 5 ns;
  signal state,nextstate: integer range 0 to 2;
  signal new_we_b,new_cs_b, new_rdy_b : bit := '1';

begin
  process(state,ads_b,w_rb,cs1)
   begin
       new_cs_b <= '1'; new_rdy_b <='1'; new_we_b <='1';
       case state is
               when 0 => 
                     if ads_b ='0' and cs1='1' then nextstate <=1;
                     else nextstate <=0;
                     end if;
               when 1 => new_cs_b <='0';nextstate <=2;
               when 2 =>
                     if w_rb ='1' then new_cs_b <='1';
                     else new_cs_b <='0';
                     end if;
                     new_rdy_b <='0';
                     nextstate <=0;
        end case;
  end process;

process(clk)
begin
   if clk='1' then state <= nextstate; end if;
end process;

we_b <=not w_rb after delay;
cs_b <=new_cs_b after delay;
rdy_b <=new_rdy_b after delay;
end behavel;