20_test_159.vhd

来自「VHDL语言100例详解」· VHDL 代码 · 共 43 行

-- Page		 	: 328 - 328
--
-- Objective 	: Solution for Test_158
--
-- File Name 	: test_159.vhd
--
-- Author    	: Joseph Pick
--


entity Test_159 is 
end Test_159;

architecture Behave_1 of Test_159 is
	signal yy : NATURAL:=55;
begin

	done:
	process
	begin
		--wait for 10 ns; 
		--STD.STANDARD.ns;
		yy <=77 after 100 ns;
		wait for 100 ns;
		yy <=  99 after 200 ns;
		wait for 300 ns;
	end process ;

	Finish:
	process
	begin
		wait for 1200 ns;
        assert false
		  report "----End of Simulation----"
		  severity error;
	end process ;

end Behave_1;