rcvr.fit.eqn

基于MAX2运用Quartus实现串口通信

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--C1_sdo is txt:inst1|sdo at LC_X1_Y8_N2
--operation mode is normal

C1_sdo_lut_out = C1L67 & (A1L21 # C1L68) # !C1L67 & (C1_no_bits_sent[0] & (C1L68) # !C1_no_bits_sent[0] & A1L21);
C1_sdo = DFFEAS(C1_sdo_lut_out, GLOBAL(C1_clk1x), VCC, , , , , , );


--B1_rbr[7] is rcvr:inst|rbr[7] at LC_X9_Y10_N7
--operation mode is normal

B1_rbr[7]_lut_out = B1_rsr[7];
B1_rbr[7] = DFFEAS(B1_rbr[7]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, , , , );


--B1_rbr[6] is rcvr:inst|rbr[6] at LC_X9_Y10_N3
--operation mode is normal

B1_rbr[6]_lut_out = B1_rsr[6];
B1_rbr[6] = DFFEAS(B1_rbr[6]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, , , , );


--B1_rbr[5] is rcvr:inst|rbr[5] at LC_X9_Y10_N2
--operation mode is normal

B1_rbr[5]_lut_out = B1_rsr[5];
B1_rbr[5] = DFFEAS(B1_rbr[5]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, , , , );


--B1_rbr[4] is rcvr:inst|rbr[4] at LC_X9_Y10_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rbr[4]_lut_out = GND;
B1_rbr[4] = DFFEAS(B1_rbr[4]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, B1_rsr[4], , , VCC);


--B1_rbr[3] is rcvr:inst|rbr[3] at LC_X9_Y10_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rbr[3]_lut_out = GND;
B1_rbr[3] = DFFEAS(B1_rbr[3]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, B1_rsr[3], , , VCC);


--B1_rbr[2] is rcvr:inst|rbr[2] at LC_X8_Y10_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rbr[2]_lut_out = GND;
B1_rbr[2] = DFFEAS(B1_rbr[2]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, B1_rsr[2], , , VCC);


--B1_rbr[1] is rcvr:inst|rbr[1] at LC_X8_Y10_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rbr[1]_lut_out = GND;
B1_rbr[1] = DFFEAS(B1_rbr[1]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, B1_rsr[1], , , VCC);


--B1_rbr[0] is rcvr:inst|rbr[0] at LC_X8_Y10_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rbr[0]_lut_out = GND;
B1_rbr[0] = DFFEAS(B1_rbr[0]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L55, B1_rsr[0], , , VCC);


--C1_no_bits_sent[1] is txt:inst1|no_bits_sent[1] at LC_X1_Y7_N8
--operation mode is normal

C1_no_bits_sent[1]_lut_out = C1_no_bits_sent[0] $ C1_no_bits_sent[1];
C1_no_bits_sent[1] = DFFEAS(C1_no_bits_sent[1]_lut_out, GLOBAL(C1_clk1x), C1_clk1x_enable, , , , , , );


--C1_no_bits_sent[3] is txt:inst1|no_bits_sent[3] at LC_X1_Y7_N3
--operation mode is normal

C1_no_bits_sent[3]_lut_out = C1_no_bits_sent[3] $ (C1_no_bits_sent[0] & C1_no_bits_sent[2] & C1_no_bits_sent[1]);
C1_no_bits_sent[3] = DFFEAS(C1_no_bits_sent[3]_lut_out, GLOBAL(C1_clk1x), C1_clk1x_enable, , , , , , );


--C1_no_bits_sent[2] is txt:inst1|no_bits_sent[2] at LC_X1_Y7_N5
--operation mode is normal

C1_no_bits_sent[2]_lut_out = C1_no_bits_sent[2] $ (C1_no_bits_sent[0] & C1_no_bits_sent[1]);
C1_no_bits_sent[2] = DFFEAS(C1_no_bits_sent[2]_lut_out, GLOBAL(C1_clk1x), C1_clk1x_enable, , , , , , );


--A1L21 is rtl~208 at LC_X1_Y8_N3
--operation mode is normal

A1L21 = !C1_no_bits_sent[2] & !C1_no_bits_sent[3] & !C1_no_bits_sent[1];


--C1_no_bits_sent[0] is txt:inst1|no_bits_sent[0] at LC_X1_Y7_N6
--operation mode is normal

C1_no_bits_sent[0]_lut_out = !C1_no_bits_sent[0];
C1_no_bits_sent[0] = DFFEAS(C1_no_bits_sent[0]_lut_out, GLOBAL(C1_clk1x), C1_clk1x_enable, , , , , , );


--C1_tsr[0] is txt:inst1|tsr[0] at LC_X1_Y7_N2
--operation mode is normal

C1_tsr[0]_lut_out = A1L20 & C1_tbr[0] # !A1L20 & (C1_tsr[1]);
C1_tsr[0] = DFFEAS(C1_tsr[0]_lut_out, GLOBAL(C1_clk1x), VCC, , C1L80, , , , );


--C1L65 is txt:inst1|sdo~498 at LC_X1_Y8_N6
--operation mode is normal

C1L65 = C1_no_bits_sent[3] & !C1_no_bits_sent[2] # !C1_no_bits_sent[3] & (C1_tsr[0]);


--C1L66 is txt:inst1|sdo~499 at LC_X1_Y8_N8
--operation mode is normal

C1L66 = C1_no_bits_sent[3] & (C1_no_bits_sent[2] # C1_tsr[0]) # !C1_no_bits_sent[3] & C1_no_bits_sent[2] & (C1_tsr[0]);


--C1L67 is txt:inst1|sdo~500 at LC_X1_Y8_N1
--operation mode is normal

C1L67 = C1L65 & (C1L66 # C1_sdo & !C1_no_bits_sent[1]) # !C1L65 & C1_sdo;


--C1L68 is txt:inst1|sdo~501 at LC_X1_Y8_N9
--operation mode is normal

C1L68 = C1L65 & (C1_no_bits_sent[1] # C1L66) # !C1L65 & C1_sdo & (C1L66);


--C1_clk1x is txt:inst1|clk1x at LC_X2_Y7_N6
--operation mode is normal

C1_clk1x_lut_out = C1_clk1x $ (A1L24 & C1_clk1x_enable);
C1_clk1x = DFFEAS(C1_clk1x_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_rsr[7] is rcvr:inst|rsr[7] at LC_X9_Y10_N8
--operation mode is normal

B1_rsr[7]_lut_out = B1_rsr[6];
B1_rsr[7] = DFFEAS(B1_rsr[7]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, , , , );


--B1_clk1x is rcvr:inst|clk1x at LC_X10_Y7_N4
--operation mode is normal

B1_clk1x_lut_out = B1_clk1x $ (A1L27 & B1_clk1x_enable);
B1_clk1x = DFFEAS(B1_clk1x_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_no_bits_rcvd[3] is rcvr:inst|no_bits_rcvd[3] at LC_X10_Y10_N0
--operation mode is normal

B1_no_bits_rcvd[3]_lut_out = B1_no_bits_rcvd[3] $ (B1_no_bits_rcvd[2] & B1_no_bits_rcvd[1] & B1_no_bits_rcvd[0]);
B1_no_bits_rcvd[3] = DFFEAS(B1_no_bits_rcvd[3]_lut_out, GLOBAL(B1_clk1x), B1_clk1x_enable, , , , , , );


--B1_no_bits_rcvd[0] is rcvr:inst|no_bits_rcvd[0] at LC_X10_Y10_N1
--operation mode is normal

B1_no_bits_rcvd[0]_lut_out = !B1_no_bits_rcvd[0];
B1_no_bits_rcvd[0] = DFFEAS(B1_no_bits_rcvd[0]_lut_out, GLOBAL(B1_clk1x), B1_clk1x_enable, , , , , , );


--B1_no_bits_rcvd[1] is rcvr:inst|no_bits_rcvd[1] at LC_X10_Y10_N4
--operation mode is normal

B1_no_bits_rcvd[1]_lut_out = B1_no_bits_rcvd[1] $ B1_no_bits_rcvd[0];
B1_no_bits_rcvd[1] = DFFEAS(B1_no_bits_rcvd[1]_lut_out, GLOBAL(B1_clk1x), B1_clk1x_enable, , , , , , );


--B1_no_bits_rcvd[2] is rcvr:inst|no_bits_rcvd[2] at LC_X10_Y10_N6
--operation mode is normal

B1_no_bits_rcvd[2]_lut_out = B1_no_bits_rcvd[2] $ (B1_no_bits_rcvd[1] & B1_no_bits_rcvd[0]);
B1_no_bits_rcvd[2] = DFFEAS(B1_no_bits_rcvd[2]_lut_out, GLOBAL(B1_clk1x), B1_clk1x_enable, , , , , , );


--B1L55 is rcvr:inst|rbr[7]~53 at LC_X9_Y10_N4
--operation mode is normal

B1L55 = !B1_no_bits_rcvd[2] & !B1_no_bits_rcvd[1] & B1_no_bits_rcvd[3] & B1_no_bits_rcvd[0];


--B1_rsr[6] is rcvr:inst|rsr[6] at LC_X10_Y10_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rsr[6]_lut_out = GND;
B1_rsr[6] = DFFEAS(B1_rsr[6]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, B1_rsr[5], , , VCC);


--B1_rsr[5] is rcvr:inst|rsr[5] at LC_X10_Y10_N5
--operation mode is normal

B1_rsr[5]_lut_out = B1_rsr[4];
B1_rsr[5] = DFFEAS(B1_rsr[5]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, , , , );


--B1_rsr[4] is rcvr:inst|rsr[4] at LC_X10_Y10_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rsr[4]_lut_out = GND;
B1_rsr[4] = DFFEAS(B1_rsr[4]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, B1_rsr[3], , , VCC);


--B1_rsr[3] is rcvr:inst|rsr[3] at LC_X10_Y10_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rsr[3]_lut_out = GND;
B1_rsr[3] = DFFEAS(B1_rsr[3]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, B1_rsr[2], , , VCC);


--B1_rsr[2] is rcvr:inst|rsr[2] at LC_X10_Y10_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rsr[2]_lut_out = GND;
B1_rsr[2] = DFFEAS(B1_rsr[2]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, B1_rsr[1], , , VCC);


--B1_rsr[1] is rcvr:inst|rsr[1] at LC_X9_Y10_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rsr[1]_lut_out = GND;
B1_rsr[1] = DFFEAS(B1_rsr[1]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, B1_rsr[0], , , VCC);


--B1_rsr[0] is rcvr:inst|rsr[0] at LC_X9_Y10_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_rsr[0]_lut_out = GND;
B1_rsr[0] = DFFEAS(B1_rsr[0]_lut_out, !GLOBAL(B1_clk1x), VCC, , B1L40, B1_rxd2, , , VCC);


--C1_clk1x_enable is txt:inst1|clk1x_enable at LC_X2_Y7_N2
--operation mode is normal

C1_clk1x_enable_lut_out = C1_wrn2 & (C1_clk1x_enable & C1L42 # !C1_wrn1) # !C1_wrn2 & C1_clk1x_enable & (C1L42);
C1_clk1x_enable = DFFEAS(C1_clk1x_enable_lut_out, B1_clk16x, VCC, , , , , , );


--C1_tbr[0] is txt:inst1|tbr[0] at LC_X1_Y5_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_tbr[0]_lut_out = GND;
C1_tbr[0] = DFFEAS(C1_tbr[0]_lut_out, !GLOBAL(wrn), VCC, , , din[0], , , VCC);


--C1_tsr[1] is txt:inst1|tsr[1] at LC_X1_Y7_N1
--operation mode is normal

C1_tsr[1]_lut_out = A1L20 & C1_tbr[1] # !A1L20 & (C1_tsr[2]);
C1_tsr[1] = DFFEAS(C1_tsr[1]_lut_out, GLOBAL(C1_clk1x), VCC, , C1L80, , , , );


--A1L20 is rtl~1 at LC_X1_Y8_N0
--operation mode is normal

A1L20 = C1_no_bits_sent[0] & !C1_no_bits_sent[2] & !C1_no_bits_sent[3] & !C1_no_bits_sent[1];


--C1L80 is txt:inst1|tsr[0]~661 at LC_X2_Y7_N7
--operation mode is normal

C1L80 = C1_no_bits_sent[3] & !C1_no_bits_sent[2] & (!C1_no_bits_sent[0] # !C1_no_bits_sent[1]) # !C1_no_bits_sent[3] & (C1_no_bits_sent[0] # C1_no_bits_sent[2]);


--C1_counter2[8] is txt:inst1|counter2[8] at LC_X2_Y8_N4
--operation mode is normal

C1_counter2[8]_lut_out = C1L1 & (!A1L22 # !C1_counter2[0] # !A1L23);
C1_counter2[8] = DFFEAS(C1_counter2[8]_lut_out, GLOBAL(clk), VCC, , C1_clk1x_enable, , , , );


--C1_counter2[7] is txt:inst1|counter2[7] at LC_X2_Y8_N1
--operation mode is normal

C1_counter2[7]_lut_out = C1L2 & (!A1L22 # !C1_counter2[0] # !A1L23);
C1_counter2[7] = DFFEAS(C1_counter2[7]_lut_out, GLOBAL(clk), VCC, , C1_clk1x_enable, , , , );


--C1_counter2[5] is txt:inst1|counter2[5] at LC_X2_Y8_N9
--operation mode is normal

C1_counter2[5]_lut_out = C1L5 & (!A1L22 # !C1_counter2[0] # !A1L23);
C1_counter2[5] = DFFEAS(C1_counter2[5]_lut_out, GLOBAL(clk), VCC, , C1_clk1x_enable, , , , );


--A1L22 is rtl~209 at LC_X2_Y8_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_counter2[6]_qfbk = C1_counter2[6];
A1L22 = C1_counter2[8] & C1_counter2[7] & !C1_counter2[6]_qfbk & C1_counter2[5];

--C1_counter2[6] is txt:inst1|counter2[6] at LC_X2_Y8_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_counter2[6] = DFFEAS(A1L22, GLOBAL(clk), VCC, , C1_clk1x_enable, C1L8, , , VCC);


--C1_counter2[4] is txt:inst1|counter2[4] at LC_X2_Y8_N6
--operation mode is normal

C1_counter2[4]_lut_out = C1L14 & (!A1L22 # !C1_counter2[0] # !A1L23);
C1_counter2[4] = DFFEAS(C1_counter2[4]_lut_out, GLOBAL(clk), VCC, , C1_clk1x_enable, , , , );


--C1_counter2[2] is txt:inst1|counter2[2] at LC_X3_Y8_N9
--operation mode is normal

C1_counter2[2]_lut_out = C1L21;
C1_counter2[2] = DFFEAS(C1_counter2[2]_lut_out, GLOBAL(clk), VCC, , C1_clk1x_enable, , , , );


--C1_counter2[1] is txt:inst1|counter2[1] at LC_X2_Y8_N0
--operation mode is normal

C1_counter2[1]_lut_out = C1L24 & (!A1L22 # !C1_counter2[0] # !A1L23);
C1_counter2[1] = DFFEAS(C1_counter2[1]_lut_out, GLOBAL(clk), VCC, , C1_clk1x_enable, , , , );


--A1L23 is rtl~210 at LC_X2_Y8_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_counter2[3]_qfbk = C1_counter2[3];
A1L23 = C1_counter2[4] & !C1_counter2[2] & !C1_counter2[3]_qfbk & !C1_counter2[1];

--C1_counter2[3] is txt:inst1|counter2[3] at LC_X2_Y8_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_counter2[3] = DFFEAS(A1L23, GLOBAL(clk), VCC, , C1_clk1x_enable, C1L18, , , VCC);


--A1L24 is rtl~211 at LC_X2_Y8_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_counter2[0]_qfbk = C1_counter2[0];
A1L24 = A1L22 & (C1_counter2[0]_qfbk & A1L23);

--C1_counter2[0] is txt:inst1|counter2[0] at LC_X2_Y8_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_counter2[0] = DFFEAS(A1L24, GLOBAL(clk), VCC, , C1_clk1x_enable, C1L11, , , VCC);


--B1L40 is rcvr:inst|LessThan~82 at LC_X10_Y10_N8
--operation mode is normal

B1L40 = !B1_no_bits_rcvd[1] & !B1_no_bits_rcvd[0] & !B1_no_bits_rcvd[2] # !B1_no_bits_rcvd[3];


--B1_clk1x_enable is rcvr:inst|clk1x_enable at LC_X9_Y7_N2
--operation mode is normal

B1_clk1x_enable_lut_out = B1_clk1x_enable # B1_rxd2 & !B1_rxd1;
B1_clk1x_enable = DFFEAS(B1_clk1x_enable_lut_out, B1_clk16x, !A1L28, , , , , , );


--B1_counter2[8] is rcvr:inst|counter2[8] at LC_X10_Y7_N3
--operation mode is normal