rcvr.map.eqn

基于MAX2运用Quartus实现串口通信

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--C1_sdo is txt:inst1|sdo
--operation mode is normal

C1_sdo_lut_out = C1L54 & (A1L21 # C1L55) # !C1L54 & (C1_no_bits_sent[0] & (C1L55) # !C1_no_bits_sent[0] & A1L21);
C1_sdo = DFFEAS(C1_sdo_lut_out, C1_clk1x, VCC, , , , , , );


--B1_rbr[7] is rcvr:inst|rbr[7]
--operation mode is normal

B1_rbr[7]_lut_out = B1_rsr[7];
B1_rbr[7] = DFFEAS(B1_rbr[7]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--B1_rbr[6] is rcvr:inst|rbr[6]
--operation mode is normal

B1_rbr[6]_lut_out = B1_rsr[6];
B1_rbr[6] = DFFEAS(B1_rbr[6]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--B1_rbr[5] is rcvr:inst|rbr[5]
--operation mode is normal

B1_rbr[5]_lut_out = B1_rsr[5];
B1_rbr[5] = DFFEAS(B1_rbr[5]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--B1_rbr[4] is rcvr:inst|rbr[4]
--operation mode is normal

B1_rbr[4]_lut_out = B1_rsr[4];
B1_rbr[4] = DFFEAS(B1_rbr[4]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--B1_rbr[3] is rcvr:inst|rbr[3]
--operation mode is normal

B1_rbr[3]_lut_out = B1_rsr[3];
B1_rbr[3] = DFFEAS(B1_rbr[3]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--B1_rbr[2] is rcvr:inst|rbr[2]
--operation mode is normal

B1_rbr[2]_lut_out = B1_rsr[2];
B1_rbr[2] = DFFEAS(B1_rbr[2]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--B1_rbr[1] is rcvr:inst|rbr[1]
--operation mode is normal

B1_rbr[1]_lut_out = B1_rsr[1];
B1_rbr[1] = DFFEAS(B1_rbr[1]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--B1_rbr[0] is rcvr:inst|rbr[0]
--operation mode is normal

B1_rbr[0]_lut_out = B1_rsr[0];
B1_rbr[0] = DFFEAS(B1_rbr[0]_lut_out, !B1_clk1x, VCC, , B1L46, , , , );


--C1_no_bits_sent[1] is txt:inst1|no_bits_sent[1]
--operation mode is normal

C1_no_bits_sent[1]_lut_out = C1_no_bits_sent[1] $ C1_no_bits_sent[0];
C1_no_bits_sent[1] = DFFEAS(C1_no_bits_sent[1]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );


--C1_no_bits_sent[3] is txt:inst1|no_bits_sent[3]
--operation mode is normal

C1_no_bits_sent[3]_lut_out = C1_no_bits_sent[3] $ (C1_no_bits_sent[1] & C1_no_bits_sent[0] & C1_no_bits_sent[2]);
C1_no_bits_sent[3] = DFFEAS(C1_no_bits_sent[3]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );


--C1_no_bits_sent[2] is txt:inst1|no_bits_sent[2]
--operation mode is normal

C1_no_bits_sent[2]_lut_out = C1_no_bits_sent[2] $ (C1_no_bits_sent[1] & C1_no_bits_sent[0]);
C1_no_bits_sent[2] = DFFEAS(C1_no_bits_sent[2]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );


--A1L21 is rtl~208
--operation mode is normal

A1L21 = !C1_no_bits_sent[1] & !C1_no_bits_sent[3] & !C1_no_bits_sent[2];


--C1_no_bits_sent[0] is txt:inst1|no_bits_sent[0]
--operation mode is normal

C1_no_bits_sent[0]_lut_out = !C1_no_bits_sent[0];
C1_no_bits_sent[0] = DFFEAS(C1_no_bits_sent[0]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );


--C1_tsr[0] is txt:inst1|tsr[0]
--operation mode is normal

C1_tsr[0]_lut_out = A1L20 & C1_tbr[0] # !A1L20 & (C1_tsr[1]);
C1_tsr[0] = DFFEAS(C1_tsr[0]_lut_out, C1_clk1x, VCC, , C1L67, , , , );


--C1L52 is txt:inst1|sdo~498
--operation mode is normal

C1L52 = C1_no_bits_sent[3] & !C1_no_bits_sent[2] # !C1_no_bits_sent[3] & (C1_tsr[0]);


--C1L53 is txt:inst1|sdo~499
--operation mode is normal

C1L53 = C1_no_bits_sent[3] & (C1_no_bits_sent[2] # C1_tsr[0]) # !C1_no_bits_sent[3] & C1_no_bits_sent[2] & C1_tsr[0];


--C1L54 is txt:inst1|sdo~500
--operation mode is normal

C1L54 = C1L52 & (C1L53 # C1_sdo & !C1_no_bits_sent[1]) # !C1L52 & C1_sdo;


--C1L55 is txt:inst1|sdo~501
--operation mode is normal

C1L55 = C1L52 & (C1_no_bits_sent[1] # C1L53) # !C1L52 & C1_sdo & (C1L53);


--C1_clk1x is txt:inst1|clk1x
--operation mode is normal

C1_clk1x_lut_out = C1_clk1x $ (C1_clk1x_enable & A1L24);
C1_clk1x = DFFEAS(C1_clk1x_lut_out, clk, VCC, , , , , , );


--B1_rsr[7] is rcvr:inst|rsr[7]
--operation mode is normal

B1_rsr[7]_lut_out = B1_rsr[6];
B1_rsr[7] = DFFEAS(B1_rsr[7]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--B1_clk1x is rcvr:inst|clk1x
--operation mode is normal

B1_clk1x_lut_out = B1_clk1x $ (B1_clk1x_enable & A1L27);
B1_clk1x = DFFEAS(B1_clk1x_lut_out, clk, VCC, , , , , , );


--B1_no_bits_rcvd[3] is rcvr:inst|no_bits_rcvd[3]
--operation mode is normal

B1_no_bits_rcvd[3]_lut_out = B1_no_bits_rcvd[3] $ (B1_no_bits_rcvd[1] & B1_no_bits_rcvd[2] & B1_no_bits_rcvd[0]);
B1_no_bits_rcvd[3] = DFFEAS(B1_no_bits_rcvd[3]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );


--B1_no_bits_rcvd[0] is rcvr:inst|no_bits_rcvd[0]
--operation mode is normal

B1_no_bits_rcvd[0]_lut_out = !B1_no_bits_rcvd[0];
B1_no_bits_rcvd[0] = DFFEAS(B1_no_bits_rcvd[0]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );


--B1_no_bits_rcvd[1] is rcvr:inst|no_bits_rcvd[1]
--operation mode is normal

B1_no_bits_rcvd[1]_lut_out = B1_no_bits_rcvd[1] $ B1_no_bits_rcvd[0];
B1_no_bits_rcvd[1] = DFFEAS(B1_no_bits_rcvd[1]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );


--B1_no_bits_rcvd[2] is rcvr:inst|no_bits_rcvd[2]
--operation mode is normal

B1_no_bits_rcvd[2]_lut_out = B1_no_bits_rcvd[2] $ (B1_no_bits_rcvd[1] & B1_no_bits_rcvd[0]);
B1_no_bits_rcvd[2] = DFFEAS(B1_no_bits_rcvd[2]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );


--B1L46 is rcvr:inst|rbr[7]~53
--operation mode is normal

B1L46 = B1_no_bits_rcvd[3] & B1_no_bits_rcvd[0] & !B1_no_bits_rcvd[1] & !B1_no_bits_rcvd[2];


--B1_rsr[6] is rcvr:inst|rsr[6]
--operation mode is normal

B1_rsr[6]_lut_out = B1_rsr[5];
B1_rsr[6] = DFFEAS(B1_rsr[6]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--B1_rsr[5] is rcvr:inst|rsr[5]
--operation mode is normal

B1_rsr[5]_lut_out = B1_rsr[4];
B1_rsr[5] = DFFEAS(B1_rsr[5]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--B1_rsr[4] is rcvr:inst|rsr[4]
--operation mode is normal

B1_rsr[4]_lut_out = B1_rsr[3];
B1_rsr[4] = DFFEAS(B1_rsr[4]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--B1_rsr[3] is rcvr:inst|rsr[3]
--operation mode is normal

B1_rsr[3]_lut_out = B1_rsr[2];
B1_rsr[3] = DFFEAS(B1_rsr[3]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--B1_rsr[2] is rcvr:inst|rsr[2]
--operation mode is normal

B1_rsr[2]_lut_out = B1_rsr[1];
B1_rsr[2] = DFFEAS(B1_rsr[2]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--B1_rsr[1] is rcvr:inst|rsr[1]
--operation mode is normal

B1_rsr[1]_lut_out = B1_rsr[0];
B1_rsr[1] = DFFEAS(B1_rsr[1]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--B1_rsr[0] is rcvr:inst|rsr[0]
--operation mode is normal

B1_rsr[0]_lut_out = B1_rxd2;
B1_rsr[0] = DFFEAS(B1_rsr[0]_lut_out, !B1_clk1x, VCC, , B1L31, , , , );


--C1_clk1x_enable is txt:inst1|clk1x_enable
--operation mode is normal

C1_clk1x_enable_lut_out = C1_clk1x_enable & (C1L29 # C1_wrn2 & !C1_wrn1) # !C1_clk1x_enable & (C1_wrn2 & !C1_wrn1);
C1_clk1x_enable = DFFEAS(C1_clk1x_enable_lut_out, B1_clk16x, VCC, , , , , , );


--C1_tbr[0] is txt:inst1|tbr[0]
--operation mode is normal

C1_tbr[0]_lut_out = din[0];
C1_tbr[0] = DFFEAS(C1_tbr[0]_lut_out, !wrn, VCC, , , , , , );


--C1_tsr[1] is txt:inst1|tsr[1]
--operation mode is normal

C1_tsr[1]_lut_out = A1L20 & C1_tbr[1] # !A1L20 & (C1_tsr[2]);
C1_tsr[1] = DFFEAS(C1_tsr[1]_lut_out, C1_clk1x, VCC, , C1L67, , , , );


--A1L20 is rtl~1
--operation mode is normal

A1L20 = C1_no_bits_sent[0] & !C1_no_bits_sent[1] & !C1_no_bits_sent[3] & !C1_no_bits_sent[2];


--C1L67 is txt:inst1|tsr[0]~661
--operation mode is normal

C1L67 = C1_no_bits_sent[3] & !C1_no_bits_sent[2] & (!C1_no_bits_sent[0] # !C1_no_bits_sent[1]) # !C1_no_bits_sent[3] & (C1_no_bits_sent[2] # C1_no_bits_sent[0]);


--C1_counter2[8] is txt:inst1|counter2[8]
--operation mode is normal

C1_counter2[8]_lut_out = C1L1 & (!A1L23 # !C1_counter2[0] # !A1L22);
C1_counter2[8] = DFFEAS(C1_counter2[8]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[7] is txt:inst1|counter2[7]
--operation mode is normal

C1_counter2[7]_lut_out = C1L2 & (!A1L23 # !C1_counter2[0] # !A1L22);
C1_counter2[7] = DFFEAS(C1_counter2[7]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[5] is txt:inst1|counter2[5]
--operation mode is normal

C1_counter2[5]_lut_out = C1L4 & (!A1L23 # !C1_counter2[0] # !A1L22);
C1_counter2[5] = DFFEAS(C1_counter2[5]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[6] is txt:inst1|counter2[6]
--operation mode is normal

C1_counter2[6]_lut_out = C1L6;
C1_counter2[6] = DFFEAS(C1_counter2[6]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--A1L22 is rtl~209
--operation mode is normal

A1L22 = C1_counter2[8] & C1_counter2[7] & C1_counter2[5] & !C1_counter2[6];


--C1_counter2[0] is txt:inst1|counter2[0]
--operation mode is normal

C1_counter2[0]_lut_out = C1L8;
C1_counter2[0] = DFFEAS(C1_counter2[0]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[4] is txt:inst1|counter2[4]
--operation mode is normal

C1_counter2[4]_lut_out = C1L10 & (!A1L23 # !C1_counter2[0] # !A1L22);
C1_counter2[4] = DFFEAS(C1_counter2[4]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[3] is txt:inst1|counter2[3]
--operation mode is normal

C1_counter2[3]_lut_out = C1L12;
C1_counter2[3] = DFFEAS(C1_counter2[3]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[2] is txt:inst1|counter2[2]
--operation mode is normal

C1_counter2[2]_lut_out = C1L14;
C1_counter2[2] = DFFEAS(C1_counter2[2]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[1] is txt:inst1|counter2[1]
--operation mode is normal

C1_counter2[1]_lut_out = C1L16 & (!A1L23 # !C1_counter2[0] # !A1L22);
C1_counter2[1] = DFFEAS(C1_counter2[1]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--A1L23 is rtl~210
--operation mode is normal

A1L23 = C1_counter2[4] & !C1_counter2[3] & !C1_counter2[2] & !C1_counter2[1];


--A1L24 is rtl~211
--operation mode is normal

A1L24 = A1L22 & C1_counter2[0] & A1L23;


--B1L31 is rcvr:inst|LessThan~82
--operation mode is normal

B1L31 = !B1_no_bits_rcvd[1] & !B1_no_bits_rcvd[2] & !B1_no_bits_rcvd[0] # !B1_no_bits_rcvd[3];


--B1_clk1x_enable is rcvr:inst|clk1x_enable
--operation mode is normal

B1_clk1x_enable_lut_out = B1_clk1x_enable # B1_rxd2 & (!B1_rxd1);
B1_clk1x_enable = DFFEAS(B1_clk1x_enable_lut_out, B1_clk16x, !A1L28, , , , , , );


--B1_counter2[8] is rcvr:inst|counter2[8]
--operation mode is normal

B1_counter2[8]_lut_out = B1L1 & (!A1L26 # !B1_counter2[0] # !A1L25);
B1_counter2[8] = DFFEAS(B1_counter2[8]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[7] is rcvr:inst|counter2[7]
--operation mode is normal

B1_counter2[7]_lut_out = B1L2 & (!A1L26 # !B1_counter2[0] # !A1L25);
B1_counter2[7] = DFFEAS(B1_counter2[7]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[5] is rcvr:inst|counter2[5]
--operation mode is normal

B1_counter2[5]_lut_out = B1L4 & (!A1L26 # !B1_counter2[0] # !A1L25);
B1_counter2[5] = DFFEAS(B1_counter2[5]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[6] is rcvr:inst|counter2[6]
--operation mode is normal

B1_counter2[6]_lut_out = B1L6;
B1_counter2[6] = DFFEAS(B1_counter2[6]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--A1L25 is rtl~212
--operation mode is normal

A1L25 = B1_counter2[8] & B1_counter2[7] & B1_counter2[5] & !B1_counter2[6];


--B1_counter2[0] is rcvr:inst|counter2[0]
--operation mode is normal

B1_counter2[0]_lut_out = B1L8;
B1_counter2[0] = DFFEAS(B1_counter2[0]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[4] is rcvr:inst|counter2[4]
--operation mode is normal

B1_counter2[4]_lut_out = B1L10 & (!A1L26 # !B1_counter2[0] # !A1L25);
B1_counter2[4] = DFFEAS(B1_counter2[4]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[3] is rcvr:inst|counter2[3]
--operation mode is normal

B1_counter2[3]_lut_out = B1L12;
B1_counter2[3] = DFFEAS(B1_counter2[3]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[2] is rcvr:inst|counter2[2]
--operation mode is normal

B1_counter2[2]_lut_out = B1L14;
B1_counter2[2] = DFFEAS(B1_counter2[2]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[1] is rcvr:inst|counter2[1]
--operation mode is normal

B1_counter2[1]_lut_out = B1L16 & (!A1L26 # !B1_counter2[0] # !A1L25);
B1_counter2[1] = DFFEAS(B1_counter2[1]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--A1L26 is rtl~213
--operation mode is normal

A1L26 = B1_counter2[4] & !B1_counter2[3] & !B1_counter2[2] & !B1_counter2[1];


--A1L27 is rtl~214
--operation mode is normal

A1L27 = A1L25 & B1_counter2[0] & A1L26;


--B1_rxd2 is rcvr:inst|rxd2
--operation mode is normal

B1_rxd2_lut_out = B1_rxd1;
B1_rxd2 = DFFEAS(B1_rxd2_lut_out, B1_clk16x, VCC, , , , , , );


--C1L29 is txt:inst1|clk1x_enable~39
--operation mode is normal

C1L29 = C1_no_bits_sent[1] # !C1_no_bits_sent[2] # !C1_no_bits_sent[3] # !C1_no_bits_sent[0];


--C1_wrn2 is txt:inst1|wrn2
--operation mode is normal

C1_wrn2_lut_out = C1_wrn1;
C1_wrn2 = DFFEAS(C1_wrn2_lut_out, B1_clk16x, VCC, , , , , , );


--C1_wrn1 is txt:inst1|wrn1
--operation mode is normal

C1_wrn1_lut_out = wrn;
C1_wrn1 = DFFEAS(C1_wrn1_lut_out, B1_clk16x, VCC, , , , , , );


--B1_clk16x is rcvr:inst|clk16x
--operation mode is normal

B1_clk16x_lut_out = B1_clk16x $ (!C1_counter1[0] & (A1L29));
B1_clk16x = DFFEAS(B1_clk16x_lut_out, clk, VCC, , , , , , );


--C1_tbr[1] is txt:inst1|tbr[1]
--operation mode is normal

C1_tbr[1]_lut_out = din[1];
C1_tbr[1] = DFFEAS(C1_tbr[1]_lut_out, !wrn, VCC, , , , , , );


--C1_tsr[2] is txt:inst1|tsr[2]
--operation mode is normal

C1_tsr[2]_lut_out = A1L20 & C1_tbr[2] # !A1L20 & (C1_tsr[3]);
C1_tsr[2] = DFFEAS(C1_tsr[2]_lut_out, C1_clk1x, VCC, , C1L67, , , , );


--C1L1 is txt:inst1|add~282
--operation mode is normal

C1L1_carry_eqn = C1L3;
C1L1 = C1_counter2[8] $ (!C1L1_carry_eqn);


--C1L2 is txt:inst1|add~287
--operation mode is arithmetic

C1L2_carry_eqn = C1L7;