rcvr.fit.qmsg

基于MAX2运用Quartus实现串口通信

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 26 11:44:00 2008 " "Info: Processing started: Thu Jun 26 11:44:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off rcvr -c rcvr " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off rcvr -c rcvr" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "rcvr EPM1270T144C5 " "Info: Selected device EPM1270T144C5 for design \"rcvr\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Info: Device EPM570T144C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Info: Device EPM570T144I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Info: Device EPM570T144A5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Info: Device EPM1270T144I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Info: Device EPM1270T144A5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 18 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 18" {  } { { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rcvr:inst\|clk1x Global clock " "Info: Automatically promoted some destinations of signal \"rcvr:inst\|clk1x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rcvr:inst\|clk1x " "Info: Destination \"rcvr:inst\|clk1x\" may be non-global or may not use global clock" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "txt:inst1\|clk1x Global clock " "Info: Automatically promoted some destinations of signal \"txt:inst1\|clk1x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "txt:inst1\|clk1x " "Info: Destination \"txt:inst1\|clk1x\" may be non-global or may not use global clock" {  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 20 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 20 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "wrn Global clock " "Info: Automatically promoted some destinations of signal \"wrn\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "txt:inst1\|wrn1 " "Info: Destination \"txt:inst1\|wrn1\" may be non-global or may not use global clock" {  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 168 0 168 184 "wrn" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "wrn " "Info: Pin \"wrn\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/program files/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/quartus/bin/pin_planner.ppl" { wrn } } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "wrn" } } } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 168 0 168 184 "wrn" "" } } } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrn } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrn } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}