rcvr.map.qmsg

基于MAX2运用Quartus实现串口通信

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 26 11:43:56 2008 " "Info: Processing started: Thu Jun 26 11:43:56 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rcvr -c rcvr " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rcvr -c rcvr" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rcvr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rcvr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rcvr-v1 " "Info: Found design unit 1: rcvr-v1" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rcvr " "Info: Found entity 1: rcvr" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file txt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 txt-v1 " "Info: Found design unit 1: txt-v1" {  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 txt " "Info: Found entity 1: txt" {  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 uart " "Info: Found entity 1: uart" {  } { { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart " "Info: Elaborating entity \"uart\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "uart " "Warning: Processing legacy GDF or BDF entity \"uart\" with Max+Plus II bus and instance naming rules" {  } { { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "txt txt:inst1 " "Info: Elaborating entity \"txt\" for hierarchy \"txt:inst1\"" {  } { { "uart.bdf" "inst1" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 152 208 320 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rcvr rcvr:inst " "Info: Elaborating entity \"rcvr\" for hierarchy \"rcvr:inst\"" {  } { { "uart.bdf" "inst" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 56 208 328 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "txt:inst1\|clk16x rcvr:inst\|clk16x " "Info: Duplicate register \"txt:inst1\|clk16x\" merged to single register \"rcvr:inst\|clk16x\"" {  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "5 5 " "Info: 5 registers lost all their fanouts during netlist optimizations. The first 5 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "rcvr:inst\|counter1\[0\] " "Info: Register \"rcvr:inst\|counter1\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "rcvr:inst\|counter1\[2\] " "Info: Register \"rcvr:inst\|counter1\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "rcvr:inst\|counter1\[1\] " "Info: Register \"rcvr:inst\|counter1\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "rcvr:inst\|counter1\[3\] " "Info: Register \"rcvr:inst\|counter1\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "rcvr:inst\|counter1\[4\] " "Info: Register \"rcvr:inst\|counter1\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "132 " "Info: Implemented 132 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "112 " "Info: Implemented 112 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 26 11:43:59 2008 " "Info: Processing ended: Thu Jun 26 11:43:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}