rcvr.tan.qmsg

基于MAX2运用Quartus实现串口通信

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[3\] rcvr:inst\|rbr\[3\] 14.206 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[3\]\" through register \"rcvr:inst\|rbr\[3\]\" is 14.206 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.536 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns rcvr:inst\|clk1x 2 REG LC_X10_Y7_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y7_N9; Fanout = 21; REG Node = 'rcvr:inst\|clk1x'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk rcvr:inst|clk1x } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.423 ns) + CELL(0.918 ns) 9.536 ns rcvr:inst\|rbr\[3\] 3 REG LC_X8_Y10_N7 1 " "Info: 3: + IC(4.423 ns) + CELL(0.918 ns) = 9.536 ns; Loc. = LC_X8_Y10_N7; Fanout = 1; REG Node = 'rcvr:inst\|rbr\[3\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.341 ns" { rcvr:inst|clk1x rcvr:inst|rbr[3] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.39 % ) " "Info: Total cell delay = 3.375 ns ( 35.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.161 ns ( 64.61 % ) " "Info: Total interconnect delay = 6.161 ns ( 64.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rbr[3] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rbr[3] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.294 ns + Longest register pin " "Info: + Longest register to pin delay is 4.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rcvr:inst\|rbr\[3\] 1 REG LC_X8_Y10_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N7; Fanout = 1; REG Node = 'rcvr:inst\|rbr\[3\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rcvr:inst|rbr[3] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.972 ns) + CELL(2.322 ns) 4.294 ns dout\[3\] 2 PIN PIN_127 0 " "Info: 2: + IC(1.972 ns) + CELL(2.322 ns) = 4.294 ns; Loc. = PIN_127; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.294 ns" { rcvr:inst|rbr[3] dout[3] } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 392 568 96 "dout\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 54.08 % ) " "Info: Total cell delay = 2.322 ns ( 54.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.972 ns ( 45.92 % ) " "Info: Total interconnect delay = 1.972 ns ( 45.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.294 ns" { rcvr:inst|rbr[3] dout[3] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "4.294 ns" { rcvr:inst|rbr[3] {} dout[3] {} } { 0.000ns 1.972ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rbr[3] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rbr[3] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.294 ns" { rcvr:inst|rbr[3] dout[3] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "4.294 ns" { rcvr:inst|rbr[3] {} dout[3] {} } { 0.000ns 1.972ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "txt:inst1\|tbr\[4\] din\[4\] wrn 3.005 ns register " "Info: th for register \"txt:inst1\|tbr\[4\]\" (data pin = \"din\[4\]\", clock pin = \"wrn\") is 3.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrn destination 7.929 ns + Longest register " "Info: + Longest clock path from clock \"wrn\" to destination register is 7.929 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns wrn 1 CLK PIN_42 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 9; CLK Node = 'wrn'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrn } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 168 0 168 184 "wrn" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.879 ns) + CELL(0.918 ns) 7.929 ns txt:inst1\|tbr\[4\] 2 REG LC_X2_Y4_N2 1 " "Info: 2: + IC(5.879 ns) + CELL(0.918 ns) = 7.929 ns; Loc. = LC_X2_Y4_N2; Fanout = 1; REG Node = 'txt:inst1\|tbr\[4\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.797 ns" { wrn txt:inst1|tbr[4] } "NODE_NAME" } } { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 25.85 % ) " "Info: Total cell delay = 2.050 ns ( 25.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.879 ns ( 74.15 % ) " "Info: Total interconnect delay = 5.879 ns ( 74.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.929 ns" { wrn txt:inst1|tbr[4] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "7.929 ns" { wrn {} wrn~combout {} txt:inst1|tbr[4] {} } { 0.000ns 0.000ns 5.879ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.145 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.145 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns din\[4\] 1 PIN PIN_38 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 1; PIN Node = 'din\[4\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[4] } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 208 0 168 224 "din\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.733 ns) + CELL(0.280 ns) 5.145 ns txt:inst1\|tbr\[4\] 2 REG LC_X2_Y4_N2 1 " "Info: 2: + IC(3.733 ns) + CELL(0.280 ns) = 5.145 ns; Loc. = LC_X2_Y4_N2; Fanout = 1; REG Node = 'txt:inst1\|tbr\[4\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.013 ns" { din[4] txt:inst1|tbr[4] } "NODE_NAME" } } { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 27.44 % ) " "Info: Total cell delay = 1.412 ns ( 27.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.733 ns ( 72.56 % ) " "Info: Total interconnect delay = 3.733 ns ( 72.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.145 ns" { din[4] txt:inst1|tbr[4] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "5.145 ns" { din[4] {} din[4]~combout {} txt:inst1|tbr[4] {} } { 0.000ns 0.000ns 3.733ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.929 ns" { wrn txt:inst1|tbr[4] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "7.929 ns" { wrn {} wrn~combout {} txt:inst1|tbr[4] {} } { 0.000ns 0.000ns 5.879ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.145 ns" { din[4] txt:inst1|tbr[4] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "5.145 ns" { din[4] {} din[4]~combout {} txt:inst1|tbr[4] {} } { 0.000ns 0.000ns 3.733ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 26 11:44:05 2008 " "Info: Processing ended: Thu Jun 26 11:44:05 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}