rcvr.tan.qmsg

基于MAX2运用Quartus实现串口通信

{ "Info" "ITAN_NO_REG2REG_EXIST" "wrn " "Info: No valid register-to-register data paths exist for clock \"wrn\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "rcvr:inst\|rxd2 rcvr:inst\|rsr\[0\] clk 19 ps " "Info: Found hold time violation between source  pin or register \"rcvr:inst\|rxd2\" and destination pin or register \"rcvr:inst\|rsr\[0\]\" for clock \"clk\" (Hold time is 19 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.405 ns + Largest " "Info: + Largest clock skew is 2.405 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.536 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns rcvr:inst\|clk1x 2 REG LC_X10_Y7_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y7_N9; Fanout = 21; REG Node = 'rcvr:inst\|clk1x'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk rcvr:inst|clk1x } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.423 ns) + CELL(0.918 ns) 9.536 ns rcvr:inst\|rsr\[0\] 3 REG LC_X8_Y10_N3 2 " "Info: 3: + IC(4.423 ns) + CELL(0.918 ns) = 9.536 ns; Loc. = LC_X8_Y10_N3; Fanout = 2; REG Node = 'rcvr:inst\|rsr\[0\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.341 ns" { rcvr:inst|clk1x rcvr:inst|rsr[0] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.39 % ) " "Info: Total cell delay = 3.375 ns ( 35.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.161 ns ( 64.61 % ) " "Info: Total interconnect delay = 6.161 ns ( 64.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rsr[0] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rsr[0] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.131 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns rcvr:inst\|clk16x 2 REG LC_X8_Y8_N6 7 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X8_Y8_N6; Fanout = 7; REG Node = 'rcvr:inst\|clk16x'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk rcvr:inst|clk16x } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.018 ns) + CELL(0.918 ns) 7.131 ns rcvr:inst\|rxd2 3 REG LC_X8_Y8_N8 2 " "Info: 3: + IC(2.018 ns) + CELL(0.918 ns) = 7.131 ns; Loc. = LC_X8_Y8_N8; Fanout = 2; REG Node = 'rcvr:inst\|rxd2'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { rcvr:inst|clk16x rcvr:inst|rxd2 } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 47.33 % ) " "Info: Total cell delay = 3.375 ns ( 47.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.756 ns ( 52.67 % ) " "Info: Total interconnect delay = 3.756 ns ( 52.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.131 ns" { clk rcvr:inst|clk16x rcvr:inst|rxd2 } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "7.131 ns" { clk {} clk~combout {} rcvr:inst|clk16x {} rcvr:inst|rxd2 {} } { 0.000ns 0.000ns 1.738ns 2.018ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rsr[0] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rsr[0] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.131 ns" { clk rcvr:inst|clk16x rcvr:inst|rxd2 } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "7.131 ns" { clk {} clk~combout {} rcvr:inst|clk16x {} rcvr:inst|rxd2 {} } { 0.000ns 0.000ns 1.738ns 2.018ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.231 ns - Shortest register register " "Info: - Shortest register to register delay is 2.231 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rcvr:inst\|rxd2 1 REG LC_X8_Y8_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y8_N8; Fanout = 2; REG Node = 'rcvr:inst\|rxd2'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rcvr:inst|rxd2 } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.951 ns) + CELL(0.280 ns) 2.231 ns rcvr:inst\|rsr\[0\] 2 REG LC_X8_Y10_N3 2 " "Info: 2: + IC(1.951 ns) + CELL(0.280 ns) = 2.231 ns; Loc. = LC_X8_Y10_N3; Fanout = 2; REG Node = 'rcvr:inst\|rsr\[0\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { rcvr:inst|rxd2 rcvr:inst|rsr[0] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 12.55 % ) " "Info: Total cell delay = 0.280 ns ( 12.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.951 ns ( 87.45 % ) " "Info: Total interconnect delay = 1.951 ns ( 87.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { rcvr:inst|rxd2 rcvr:inst|rsr[0] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.231 ns" { rcvr:inst|rxd2 {} rcvr:inst|rsr[0] {} } { 0.000ns 1.951ns } { 0.000ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 17 -1 0 } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rsr[0] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rsr[0] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.131 ns" { clk rcvr:inst|clk16x rcvr:inst|rxd2 } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "7.131 ns" { clk {} clk~combout {} rcvr:inst|clk16x {} rcvr:inst|rxd2 {} } { 0.000ns 0.000ns 1.738ns 2.018ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { rcvr:inst|rxd2 rcvr:inst|rsr[0] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.231 ns" { rcvr:inst|rxd2 {} rcvr:inst|rsr[0] {} } { 0.000ns 1.951ns } { 0.000ns 0.280ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "rcvr:inst\|rxd1 rxd clk -1.162 ns register " "Info: tsu for register \"rcvr:inst\|rxd1\" (data pin = \"rxd\", clock pin = \"clk\") is -1.162 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.636 ns + Longest pin register " "Info: + Longest pin to register delay is 5.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rxd 1 PIN PIN_8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_8; Fanout = 1; PIN Node = 'rxd'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 96 0 168 112 "rxd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.224 ns) + CELL(0.280 ns) 5.636 ns rcvr:inst\|rxd1 2 REG LC_X8_Y8_N5 2 " "Info: 2: + IC(4.224 ns) + CELL(0.280 ns) = 5.636 ns; Loc. = LC_X8_Y8_N5; Fanout = 2; REG Node = 'rcvr:inst\|rxd1'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.504 ns" { rxd rcvr:inst|rxd1 } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 25.05 % ) " "Info: Total cell delay = 1.412 ns ( 25.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.224 ns ( 74.95 % ) " "Info: Total interconnect delay = 4.224 ns ( 74.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.636 ns" { rxd rcvr:inst|rxd1 } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "5.636 ns" { rxd {} rxd~combout {} rcvr:inst|rxd1 {} } { 0.000ns 0.000ns 4.224ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.131 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns rcvr:inst\|clk16x 2 REG LC_X8_Y8_N6 7 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X8_Y8_N6; Fanout = 7; REG Node = 'rcvr:inst\|clk16x'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk rcvr:inst|clk16x } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.018 ns) + CELL(0.918 ns) 7.131 ns rcvr:inst\|rxd1 3 REG LC_X8_Y8_N5 2 " "Info: 3: + IC(2.018 ns) + CELL(0.918 ns) = 7.131 ns; Loc. = LC_X8_Y8_N5; Fanout = 2; REG Node = 'rcvr:inst\|rxd1'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { rcvr:inst|clk16x rcvr:inst|rxd1 } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 47.33 % ) " "Info: Total cell delay = 3.375 ns ( 47.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.756 ns ( 52.67 % ) " "Info: Total interconnect delay = 3.756 ns ( 52.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.131 ns" { clk rcvr:inst|clk16x rcvr:inst|rxd1 } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "7.131 ns" { clk {} clk~combout {} rcvr:inst|clk16x {} rcvr:inst|rxd1 {} } { 0.000ns 0.000ns 1.738ns 2.018ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.636 ns" { rxd rcvr:inst|rxd1 } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "5.636 ns" { rxd {} rxd~combout {} rcvr:inst|rxd1 {} } { 0.000ns 0.000ns 4.224ns } { 0.000ns 1.132ns 0.280ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.131 ns" { clk rcvr:inst|clk16x rcvr:inst|rxd1 } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "7.131 ns" { clk {} clk~combout {} rcvr:inst|clk16x {} rcvr:inst|rxd1 {} } { 0.000ns 0.000ns 1.738ns 2.018ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}