rcvr.tan.qmsg

基于MAX2运用Quartus实现串口通信

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wrn " "Info: Assuming node \"wrn\" is an undefined clock" {  } { { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 168 0 168 184 "wrn" "" } } } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "wrn" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "rcvr:inst\|clk16x " "Info: Detected ripple clock \"rcvr:inst\|clk16x\" as buffer" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "rcvr:inst\|clk16x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "rcvr:inst\|clk1x " "Info: Detected ripple clock \"rcvr:inst\|clk1x\" as buffer" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "rcvr:inst\|clk1x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "txt:inst1\|clk1x " "Info: Detected ripple clock \"txt:inst1\|clk1x\" as buffer" {  } { { "txt.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/txt.vhd" 20 -1 0 } } { "c:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "txt:inst1\|clk1x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register rcvr:inst\|no_bits_rcvd\[1\] register rcvr:inst\|rsr\[7\] 100.08 MHz 9.992 ns Internal " "Info: Clock \"clk\" has Internal fmax of 100.08 MHz between source register \"rcvr:inst\|no_bits_rcvd\[1\]\" and destination register \"rcvr:inst\|rsr\[7\]\" (period= 9.992 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.287 ns + Longest register register " "Info: + Longest register to register delay is 4.287 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rcvr:inst\|no_bits_rcvd\[1\] 1 REG LC_X9_Y10_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y10_N5; Fanout = 6; REG Node = 'rcvr:inst\|no_bits_rcvd\[1\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rcvr:inst|no_bits_rcvd[1] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.914 ns) 1.954 ns rcvr:inst\|LessThan1~64 2 COMB LC_X9_Y10_N1 8 " "Info: 2: + IC(1.040 ns) + CELL(0.914 ns) = 1.954 ns; Loc. = LC_X9_Y10_N1; Fanout = 8; COMB Node = 'rcvr:inst\|LessThan1~64'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.954 ns" { rcvr:inst|no_bits_rcvd[1] rcvr:inst|LessThan1~64 } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(1.243 ns) 4.287 ns rcvr:inst\|rsr\[7\] 3 REG LC_X10_Y10_N4 1 " "Info: 3: + IC(1.090 ns) + CELL(1.243 ns) = 4.287 ns; Loc. = LC_X10_Y10_N4; Fanout = 1; REG Node = 'rcvr:inst\|rsr\[7\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.333 ns" { rcvr:inst|LessThan1~64 rcvr:inst|rsr[7] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.157 ns ( 50.31 % ) " "Info: Total cell delay = 2.157 ns ( 50.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.130 ns ( 49.69 % ) " "Info: Total interconnect delay = 2.130 ns ( 49.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.287 ns" { rcvr:inst|no_bits_rcvd[1] rcvr:inst|LessThan1~64 rcvr:inst|rsr[7] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "4.287 ns" { rcvr:inst|no_bits_rcvd[1] {} rcvr:inst|LessThan1~64 {} rcvr:inst|rsr[7] {} } { 0.000ns 1.040ns 1.090ns } { 0.000ns 0.914ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.536 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 9.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns rcvr:inst\|clk1x 2 REG LC_X10_Y7_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y7_N9; Fanout = 21; REG Node = 'rcvr:inst\|clk1x'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk rcvr:inst|clk1x } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.423 ns) + CELL(0.918 ns) 9.536 ns rcvr:inst\|rsr\[7\] 3 REG LC_X10_Y10_N4 1 " "Info: 3: + IC(4.423 ns) + CELL(0.918 ns) = 9.536 ns; Loc. = LC_X10_Y10_N4; Fanout = 1; REG Node = 'rcvr:inst\|rsr\[7\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.341 ns" { rcvr:inst|clk1x rcvr:inst|rsr[7] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.39 % ) " "Info: Total cell delay = 3.375 ns ( 35.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.161 ns ( 64.61 % ) " "Info: Total interconnect delay = 6.161 ns ( 64.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rsr[7] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rsr[7] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.536 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart.bdf" "" { Schematic "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns rcvr:inst\|clk1x 2 REG LC_X10_Y7_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y7_N9; Fanout = 21; REG Node = 'rcvr:inst\|clk1x'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk rcvr:inst|clk1x } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.423 ns) + CELL(0.918 ns) 9.536 ns rcvr:inst\|no_bits_rcvd\[1\] 3 REG LC_X9_Y10_N5 6 " "Info: 3: + IC(4.423 ns) + CELL(0.918 ns) = 9.536 ns; Loc. = LC_X9_Y10_N5; Fanout = 6; REG Node = 'rcvr:inst\|no_bits_rcvd\[1\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.341 ns" { rcvr:inst|clk1x rcvr:inst|no_bits_rcvd[1] } "NODE_NAME" } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.39 % ) " "Info: Total cell delay = 3.375 ns ( 35.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.161 ns ( 64.61 % ) " "Info: Total interconnect delay = 6.161 ns ( 64.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|no_bits_rcvd[1] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|no_bits_rcvd[1] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rsr[7] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rsr[7] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|no_bits_rcvd[1] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|no_bits_rcvd[1] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 89 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 89 -1 0 } } { "rcvr.vhd" "" { Text "F:/\[Studio\]/CPLD Competition/光盘/例程/Serial/rcvr.vhd" 75 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.287 ns" { rcvr:inst|no_bits_rcvd[1] rcvr:inst|LessThan1~64 rcvr:inst|rsr[7] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "4.287 ns" { rcvr:inst|no_bits_rcvd[1] {} rcvr:inst|LessThan1~64 {} rcvr:inst|rsr[7] {} } { 0.000ns 1.040ns 1.090ns } { 0.000ns 0.914ns 1.243ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|rsr[7] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|rsr[7] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.536 ns" { clk rcvr:inst|clk1x rcvr:inst|no_bits_rcvd[1] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.536 ns" { clk {} clk~combout {} rcvr:inst|clk1x {} rcvr:inst|no_bits_rcvd[1] {} } { 0.000ns 0.000ns 1.738ns 4.423ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}