rcvr.sim.rpt

基于MAX2运用Quartus实现串口通信

; |rcvr|rbr[3]          ; |rcvr|rbr[3]                 ; regout           ;
; |rcvr|rbr[4]          ; |rcvr|rbr[4]                 ; regout           ;
; |rcvr|rbr[5]          ; |rcvr|rbr[5]                 ; regout           ;
; |rcvr|rbr[6]          ; |rcvr|rbr[6]                 ; regout           ;
; |rcvr|rbr[7]          ; |rcvr|rbr[7]                 ; regout           ;
; |rcvr|rsr[0]          ; |rcvr|rsr[0]                 ; regout           ;
; |rcvr|clk1x           ; |rcvr|clk1x                  ; regout           ;
; |rcvr|no_bits_rcvd[0] ; |rcvr|no_bits_rcvd[0]        ; regout           ;
; |rcvr|no_bits_rcvd[1] ; |rcvr|no_bits_rcvd[1]        ; regout           ;
; |rcvr|no_bits_rcvd[2] ; |rcvr|no_bits_rcvd[2]        ; regout           ;
; |rcvr|rbr[0]~53       ; |rcvr|rbr[0]~53              ; combout          ;
; |rcvr|rsr[1]          ; |rcvr|rsr[1]                 ; regout           ;
; |rcvr|rsr[2]          ; |rcvr|rsr[2]                 ; regout           ;
; |rcvr|rsr[3]          ; |rcvr|rsr[3]                 ; regout           ;
; |rcvr|rsr[4]          ; |rcvr|rsr[4]                 ; regout           ;
; |rcvr|rsr[5]          ; |rcvr|rsr[5]                 ; regout           ;
; |rcvr|rsr[6]          ; |rcvr|rsr[6]                 ; regout           ;
; |rcvr|rsr[7]          ; |rcvr|rsr[7]                 ; regout           ;
; |rcvr|LessThan~82     ; |rcvr|LessThan~82            ; combout          ;
; |rcvr|counter2[3]     ; |rcvr|counter2[3]            ; regout           ;
; |rcvr|counter2[3]     ; |rcvr|counter2[3]~58         ; cout0            ;
; |rcvr|counter2[3]     ; |rcvr|counter2[3]~58COUT1_87 ; cout1            ;
; |rcvr|counter2[4]     ; |rcvr|counter2[4]            ; regout           ;
; |rcvr|counter2[0]     ; |rcvr|counter2[0]~66         ; cout0            ;
; |rcvr|counter2[0]     ; |rcvr|counter2[0]~66COUT1_82 ; cout1            ;
; |rcvr|counter2[1]     ; |rcvr|counter2[1]~70         ; cout0            ;
; |rcvr|counter2[1]     ; |rcvr|counter2[1]~70COUT1_83 ; cout1            ;
; |rcvr|counter2[2]     ; |rcvr|counter2[2]~74         ; cout0            ;
; |rcvr|counter2[2]     ; |rcvr|counter2[2]~74COUT1_85 ; cout1            ;
; |rcvr|clk1x_enable    ; |rcvr|clk1x_enable           ; regout           ;
; |rcvr|clk1x~40        ; |rcvr|clk1x~40               ; combout          ;
; |rcvr|rtl~20          ; |rcvr|rtl~20                 ; combout          ;
; |rcvr|dout[0]         ; |rcvr|dout[0]                ; padio            ;
; |rcvr|dout[1]         ; |rcvr|dout[1]                ; padio            ;
; |rcvr|dout[2]         ; |rcvr|dout[2]                ; padio            ;
; |rcvr|dout[3]         ; |rcvr|dout[3]                ; padio            ;
; |rcvr|dout[4]         ; |rcvr|dout[4]                ; padio            ;
; |rcvr|dout[5]         ; |rcvr|dout[5]                ; padio            ;
; |rcvr|dout[6]         ; |rcvr|dout[6]                ; padio            ;
; |rcvr|dout[7]         ; |rcvr|dout[7]                ; padio            ;
+-----------------------+------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                ;
+-----------------------+------------------------------+------------------+
; Node Name             ; Output Port Name             ; Output Port Type ;
+-----------------------+------------------------------+------------------+
; |rcvr|rbr[0]          ; |rcvr|rbr[0]                 ; regout           ;
; |rcvr|rbr[1]          ; |rcvr|rbr[1]                 ; regout           ;
; |rcvr|rbr[2]          ; |rcvr|rbr[2]                 ; regout           ;
; |rcvr|rbr[3]          ; |rcvr|rbr[3]                 ; regout           ;
; |rcvr|rbr[4]          ; |rcvr|rbr[4]                 ; regout           ;
; |rcvr|rbr[5]          ; |rcvr|rbr[5]                 ; regout           ;
; |rcvr|rbr[6]          ; |rcvr|rbr[6]                 ; regout           ;
; |rcvr|rbr[7]          ; |rcvr|rbr[7]                 ; regout           ;
; |rcvr|rsr[0]          ; |rcvr|rsr[0]                 ; regout           ;
; |rcvr|clk1x           ; |rcvr|clk1x                  ; regout           ;
; |rcvr|no_bits_rcvd[0] ; |rcvr|no_bits_rcvd[0]        ; regout           ;
; |rcvr|no_bits_rcvd[1] ; |rcvr|no_bits_rcvd[1]        ; regout           ;
; |rcvr|no_bits_rcvd[2] ; |rcvr|no_bits_rcvd[2]        ; regout           ;
; |rcvr|rbr[0]~53       ; |rcvr|rbr[0]~53              ; combout          ;
; |rcvr|rsr[1]          ; |rcvr|rsr[1]                 ; regout           ;
; |rcvr|rsr[2]          ; |rcvr|rsr[2]                 ; regout           ;
; |rcvr|rsr[3]          ; |rcvr|rsr[3]                 ; regout           ;
; |rcvr|rsr[4]          ; |rcvr|rsr[4]                 ; regout           ;
; |rcvr|rsr[5]          ; |rcvr|rsr[5]                 ; regout           ;
; |rcvr|rsr[6]          ; |rcvr|rsr[6]                 ; regout           ;
; |rcvr|rsr[7]          ; |rcvr|rsr[7]                 ; regout           ;
; |rcvr|rxd2            ; |rcvr|rxd2                   ; regout           ;
; |rcvr|LessThan~82     ; |rcvr|LessThan~82            ; combout          ;
; |rcvr|counter2[3]     ; |rcvr|counter2[3]            ; regout           ;
; |rcvr|counter2[3]     ; |rcvr|counter2[3]~58         ; cout0            ;
; |rcvr|counter2[3]     ; |rcvr|counter2[3]~58COUT1_87 ; cout1            ;
; |rcvr|counter2[4]     ; |rcvr|counter2[4]            ; regout           ;
; |rcvr|counter2[0]     ; |rcvr|counter2[0]~66         ; cout0            ;
; |rcvr|counter2[0]     ; |rcvr|counter2[0]~66COUT1_82 ; cout1            ;
; |rcvr|counter2[1]     ; |rcvr|counter2[1]~70         ; cout0            ;
; |rcvr|counter2[1]     ; |rcvr|counter2[1]~70COUT1_83 ; cout1            ;
; |rcvr|counter2[2]     ; |rcvr|counter2[2]~74         ; cout0            ;
; |rcvr|counter2[2]     ; |rcvr|counter2[2]~74COUT1_85 ; cout1            ;
; |rcvr|clk1x_enable    ; |rcvr|clk1x_enable           ; regout           ;
; |rcvr|clk1x~40        ; |rcvr|clk1x~40               ; combout          ;
; |rcvr|rxd1            ; |rcvr|rxd1                   ; regout           ;
; |rcvr|rtl~20          ; |rcvr|rtl~20                 ; combout          ;
; |rcvr|dout[0]         ; |rcvr|dout[0]                ; padio            ;
; |rcvr|dout[1]         ; |rcvr|dout[1]                ; padio            ;
; |rcvr|dout[2]         ; |rcvr|dout[2]                ; padio            ;
; |rcvr|dout[3]         ; |rcvr|dout[3]                ; padio            ;
; |rcvr|dout[4]         ; |rcvr|dout[4]                ; padio            ;
; |rcvr|dout[5]         ; |rcvr|dout[5]                ; padio            ;
; |rcvr|dout[6]         ; |rcvr|dout[6]                ; padio            ;
; |rcvr|dout[7]         ; |rcvr|dout[7]                ; padio            ;
+-----------------------+------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Feb 06 17:36:06 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off rcvr -c rcvr
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is       8.16 %
Info: Number of transitions in simulation is 353
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Feb 06 17:36:06 2007
    Info: Elapsed time: 00:00:01