prev_cmp_lcdcont.fit.qmsg

运用Quartus在LCM中显示静态宫殿图形

{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.747 ns register pin " "Info: Estimated most critical path is register to pin delay of 4.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd0:mylcd\|lcd_data\[5\] 1 REG LAB_X13_Y7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y7; Fanout = 2; REG Node = 'lcd0:mylcd\|lcd_data\[5\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd0:mylcd|lcd_data[5] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.425 ns) + CELL(2.322 ns) 4.747 ns data_out\[5\] 2 PIN PIN_110 0 " "Info: 2: + IC(2.425 ns) + CELL(2.322 ns) = 4.747 ns; Loc. = PIN_110; Fanout = 0; PIN Node = 'data_out\[5\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.747 ns" { lcd0:mylcd|lcd_data[5] data_out[5] } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 48.92 % ) " "Info: Total cell delay = 2.322 ns ( 48.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.425 ns ( 51.08 % ) " "Info: Total interconnect delay = 2.425 ns ( 51.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.747 ns" { lcd0:mylcd|lcd_data[5] data_out[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X9_Y0 X17_Y11 " "Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "rw_out GND " "Info: Pin rw_out has GND driving its datain port" {  } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { rw_out } } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rw_out" } } } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 10 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rw_out } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rw_out } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cont GND " "Info: Pin cont has GND driving its datain port" {  } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { cont } } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "cont" } } } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 10 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cont } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cont } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.fit.smsg " "Info: Generated suppressed messages file E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "166 " "Info: Allocated 166 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 17 10:22:38 2008 " "Info: Processing ended: Tue Jun 17 10:22:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}