prev_cmp_lcdcont.map.qmsg

运用Quartus在LCM中显示静态宫殿图形

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 17 10:22:30 2008 " "Info: Processing started: Tue Jun 17 10:22:30 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcdcont -c lcdcont " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcdcont -c lcdcont" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdiv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clockdiv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clockdiv-behavioural " "Info: Found design unit 1: clockdiv-behavioural" {  } { { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clockdiv " "Info: Found entity 1: clockdiv" {  } { { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdcont.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcdcont.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcdcont-structural " "Info: Found design unit 1: lcdcont-structural" {  } { { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lcdcont " "Info: Found entity 1: lcdcont" {  } { { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcd0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd0-behavioural " "Info: Found design unit 1: lcd0-behavioural" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd0 " "Info: Found entity 1: lcd0" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcdcont " "Info: Elaborating entity \"lcdcont\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset lcdcont.vhd(49) " "Warning (10492): VHDL Process Statement warning at lcdcont.vhd(49): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 49 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd0 lcd0:mylcd " "Info: Elaborating entity \"lcd0\" for hierarchy \"lcd0:mylcd\"" {  } { { "lcdcont.vhd" "mylcd" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 62 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clockdiv clockdiv:div " "Info: Elaborating entity \"clockdiv\" for hierarchy \"clockdiv:div\"" {  } { { "lcdcont.vhd" "div" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 72 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "lcd0:mylcd\|write_mode High " "Info: Power-up level of register \"lcd0:mylcd\|write_mode\" is not specified -- using power-up level of High to minimize register" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 36 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd0:mylcd\|write_mode data_in VCC " "Warning (14130): Reduced register \"lcd0:mylcd\|write_mode\" with stuck data_in port to stuck value VCC" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 36 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}