prev_cmp_lcdcont.tan.qmsg

运用Quartus在LCM中显示静态宫殿图形

{ "Info" "ITDB_TH_RESULT" "lcd0:mylcd\|count1\[0\] reset clk 2.594 ns register " "Info: th for register \"lcd0:mylcd\|count1\[0\]\" (data pin = \"reset\", clock pin = \"clk\") is 2.594 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.175 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clock_int 2 REG LC_X12_Y3_N0 35 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N0; Fanout = 35; REG Node = 'clockdiv:div\|clock_int'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv:div|clock_int } "NODE_NAME" } } { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.918 ns) 8.175 ns lcd0:mylcd\|count1\[0\] 3 REG LC_X12_Y8_N6 22 " "Info: 3: + IC(3.062 ns) + CELL(0.918 ns) = 8.175 ns; Loc. = LC_X12_Y8_N6; Fanout = 22; REG Node = 'lcd0:mylcd\|count1\[0\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.980 ns" { clockdiv:div|clock_int lcd0:mylcd|count1[0] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.28 % ) " "Info: Total cell delay = 3.375 ns ( 41.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 58.72 % ) " "Info: Total interconnect delay = 4.800 ns ( 58.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|count1[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|count1[0] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.802 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_42 28 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 28; PIN Node = 'reset'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.079 ns) + CELL(0.591 ns) 5.802 ns lcd0:mylcd\|count1\[0\] 2 REG LC_X12_Y8_N6 22 " "Info: 2: + IC(4.079 ns) + CELL(0.591 ns) = 5.802 ns; Loc. = LC_X12_Y8_N6; Fanout = 22; REG Node = 'lcd0:mylcd\|count1\[0\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.670 ns" { reset lcd0:mylcd|count1[0] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 29.70 % ) " "Info: Total cell delay = 1.723 ns ( 29.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.079 ns ( 70.30 % ) " "Info: Total interconnect delay = 4.079 ns ( 70.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.802 ns" { reset lcd0:mylcd|count1[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.802 ns" { reset {} reset~combout {} lcd0:mylcd|count1[0] {} } { 0.000ns 0.000ns 4.079ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|count1[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|count1[0] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.802 ns" { reset lcd0:mylcd|count1[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.802 ns" { reset {} reset~combout {} lcd0:mylcd|count1[0] {} } { 0.000ns 0.000ns 4.079ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 17 10:22:42 2008 " "Info: Processing ended: Tue Jun 17 10:22:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}