prev_cmp_lcdcont.tan.qmsg

运用Quartus在LCM中显示静态宫殿图形

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clockdiv:div\|clock_int " "Info: Detected ripple clock \"clockdiv:div\|clock_int\" as buffer" {  } { { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 25 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clockdiv:div\|clock_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd0:mylcd\|count1\[1\] register lcd0:mylcd\|lcd_data\[1\] 110.93 MHz 9.015 ns Internal " "Info: Clock \"clk\" has Internal fmax of 110.93 MHz between source register \"lcd0:mylcd\|count1\[1\]\" and destination register \"lcd0:mylcd\|lcd_data\[1\]\" (period= 9.015 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.306 ns + Longest register register " "Info: + Longest register to register delay is 8.306 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd0:mylcd\|count1\[1\] 1 REG LC_X12_Y8_N1 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N1; Fanout = 21; REG Node = 'lcd0:mylcd\|count1\[1\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd0:mylcd|count1[1] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.047 ns) + CELL(0.200 ns) 2.247 ns lcd0:mylcd\|Equal3~55 2 COMB LC_X12_Y8_N3 1 " "Info: 2: + IC(2.047 ns) + CELL(0.200 ns) = 2.247 ns; Loc. = LC_X12_Y8_N3; Fanout = 1; COMB Node = 'lcd0:mylcd\|Equal3~55'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.247 ns" { lcd0:mylcd|count1[1] lcd0:mylcd|Equal3~55 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 2.752 ns lcd0:mylcd\|Equal3~56 3 COMB LC_X12_Y8_N4 8 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 2.752 ns; Loc. = LC_X12_Y8_N4; Fanout = 8; COMB Node = 'lcd0:mylcd\|Equal3~56'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { lcd0:mylcd|Equal3~55 lcd0:mylcd|Equal3~56 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.511 ns) 4.108 ns lcd0:mylcd\|count1\[0\]~334 4 COMB LC_X12_Y8_N2 4 " "Info: 4: + IC(0.845 ns) + CELL(0.511 ns) = 4.108 ns; Loc. = LC_X12_Y8_N2; Fanout = 4; COMB Node = 'lcd0:mylcd\|count1\[0\]~334'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.356 ns" { lcd0:mylcd|Equal3~56 lcd0:mylcd|count1[0]~334 } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.562 ns) + CELL(0.740 ns) 7.410 ns lcd0:mylcd\|Selector8~358 5 COMB LC_X14_Y8_N6 1 " "Info: 5: + IC(2.562 ns) + CELL(0.740 ns) = 7.410 ns; Loc. = LC_X14_Y8_N6; Fanout = 1; COMB Node = 'lcd0:mylcd\|Selector8~358'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.302 ns" { lcd0:mylcd|count1[0]~334 lcd0:mylcd|Selector8~358 } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 8.306 ns lcd0:mylcd\|lcd_data\[1\] 6 REG LC_X14_Y8_N7 2 " "Info: 6: + IC(0.305 ns) + CELL(0.591 ns) = 8.306 ns; Loc. = LC_X14_Y8_N7; Fanout = 2; REG Node = 'lcd0:mylcd\|lcd_data\[1\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { lcd0:mylcd|Selector8~358 lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.242 ns ( 26.99 % ) " "Info: Total cell delay = 2.242 ns ( 26.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.064 ns ( 73.01 % ) " "Info: Total interconnect delay = 6.064 ns ( 73.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.306 ns" { lcd0:mylcd|count1[1] lcd0:mylcd|Equal3~55 lcd0:mylcd|Equal3~56 lcd0:mylcd|count1[0]~334 lcd0:mylcd|Selector8~358 lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.306 ns" { lcd0:mylcd|count1[1] {} lcd0:mylcd|Equal3~55 {} lcd0:mylcd|Equal3~56 {} lcd0:mylcd|count1[0]~334 {} lcd0:mylcd|Selector8~358 {} lcd0:mylcd|lcd_data[1] {} } { 0.000ns 2.047ns 0.305ns 0.845ns 2.562ns 0.305ns } { 0.000ns 0.200ns 0.200ns 0.511ns 0.740ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.175 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clock_int 2 REG LC_X12_Y3_N0 35 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N0; Fanout = 35; REG Node = 'clockdiv:div\|clock_int'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv:div|clock_int } "NODE_NAME" } } { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.918 ns) 8.175 ns lcd0:mylcd\|lcd_data\[1\] 3 REG LC_X14_Y8_N7 2 " "Info: 3: + IC(3.062 ns) + CELL(0.918 ns) = 8.175 ns; Loc. = LC_X14_Y8_N7; Fanout = 2; REG Node = 'lcd0:mylcd\|lcd_data\[1\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.980 ns" { clockdiv:div|clock_int lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.28 % ) " "Info: Total cell delay = 3.375 ns ( 41.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 58.72 % ) " "Info: Total interconnect delay = 4.800 ns ( 58.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|lcd_data[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.175 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clock_int 2 REG LC_X12_Y3_N0 35 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N0; Fanout = 35; REG Node = 'clockdiv:div\|clock_int'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv:div|clock_int } "NODE_NAME" } } { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.918 ns) 8.175 ns lcd0:mylcd\|count1\[1\] 3 REG LC_X12_Y8_N1 21 " "Info: 3: + IC(3.062 ns) + CELL(0.918 ns) = 8.175 ns; Loc. = LC_X12_Y8_N1; Fanout = 21; REG Node = 'lcd0:mylcd\|count1\[1\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.980 ns" { clockdiv:div|clock_int lcd0:mylcd|count1[1] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.28 % ) " "Info: Total cell delay = 3.375 ns ( 41.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 58.72 % ) " "Info: Total interconnect delay = 4.800 ns ( 58.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|count1[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|count1[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|lcd_data[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|count1[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|count1[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.306 ns" { lcd0:mylcd|count1[1] lcd0:mylcd|Equal3~55 lcd0:mylcd|Equal3~56 lcd0:mylcd|count1[0]~334 lcd0:mylcd|Selector8~358 lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.306 ns" { lcd0:mylcd|count1[1] {} lcd0:mylcd|Equal3~55 {} lcd0:mylcd|Equal3~56 {} lcd0:mylcd|count1[0]~334 {} lcd0:mylcd|Selector8~358 {} lcd0:mylcd|lcd_data[1] {} } { 0.000ns 2.047ns 0.305ns 0.845ns 2.562ns 0.305ns } { 0.000ns 0.200ns 0.200ns 0.511ns 0.740ns 0.591ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|lcd_data[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|count1[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|count1[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lcd0:mylcd\|count1\[4\] reset clk -0.092 ns register " "Info: tsu for register \"lcd0:mylcd\|count1\[4\]\" (data pin = \"reset\", clock pin = \"clk\") is -0.092 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.750 ns + Longest pin register " "Info: + Longest pin to register delay is 7.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_42 28 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 28; PIN Node = 'reset'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.080 ns) + CELL(0.200 ns) 5.412 ns lcd0:mylcd\|count1\[0\]~336 2 COMB LC_X12_Y8_N5 6 " "Info: 2: + IC(4.080 ns) + CELL(0.200 ns) = 5.412 ns; Loc. = LC_X12_Y8_N5; Fanout = 6; COMB Node = 'lcd0:mylcd\|count1\[0\]~336'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.280 ns" { reset lcd0:mylcd|count1[0]~336 } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(1.243 ns) 7.750 ns lcd0:mylcd\|count1\[4\] 3 REG LC_X13_Y8_N1 14 " "Info: 3: + IC(1.095 ns) + CELL(1.243 ns) = 7.750 ns; Loc. = LC_X13_Y8_N1; Fanout = 14; REG Node = 'lcd0:mylcd\|count1\[4\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.338 ns" { lcd0:mylcd|count1[0]~336 lcd0:mylcd|count1[4] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.575 ns ( 33.23 % ) " "Info: Total cell delay = 2.575 ns ( 33.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.175 ns ( 66.77 % ) " "Info: Total interconnect delay = 5.175 ns ( 66.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.750 ns" { reset lcd0:mylcd|count1[0]~336 lcd0:mylcd|count1[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.750 ns" { reset {} reset~combout {} lcd0:mylcd|count1[0]~336 {} lcd0:mylcd|count1[4] {} } { 0.000ns 0.000ns 4.080ns 1.095ns } { 0.000ns 1.132ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.175 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clock_int 2 REG LC_X12_Y3_N0 35 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N0; Fanout = 35; REG Node = 'clockdiv:div\|clock_int'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv:div|clock_int } "NODE_NAME" } } { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.918 ns) 8.175 ns lcd0:mylcd\|count1\[4\] 3 REG LC_X13_Y8_N1 14 " "Info: 3: + IC(3.062 ns) + CELL(0.918 ns) = 8.175 ns; Loc. = LC_X13_Y8_N1; Fanout = 14; REG Node = 'lcd0:mylcd\|count1\[4\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.980 ns" { clockdiv:div|clock_int lcd0:mylcd|count1[4] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.28 % ) " "Info: Total cell delay = 3.375 ns ( 41.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 58.72 % ) " "Info: Total interconnect delay = 4.800 ns ( 58.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|count1[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|count1[4] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.750 ns" { reset lcd0:mylcd|count1[0]~336 lcd0:mylcd|count1[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.750 ns" { reset {} reset~combout {} lcd0:mylcd|count1[0]~336 {} lcd0:mylcd|count1[4] {} } { 0.000ns 0.000ns 4.080ns 1.095ns } { 0.000ns 1.132ns 0.200ns 1.243ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|count1[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|count1[4] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data_out\[1\] lcd0:mylcd\|lcd_data\[1\] 13.518 ns register " "Info: tco from clock \"clk\" to destination pin \"data_out\[1\]\" through register \"lcd0:mylcd\|lcd_data\[1\]\" is 13.518 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.175 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clock_int 2 REG LC_X12_Y3_N0 35 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N0; Fanout = 35; REG Node = 'clockdiv:div\|clock_int'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv:div|clock_int } "NODE_NAME" } } { "clockdiv.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/clockdiv.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.918 ns) 8.175 ns lcd0:mylcd\|lcd_data\[1\] 3 REG LC_X14_Y8_N7 2 " "Info: 3: + IC(3.062 ns) + CELL(0.918 ns) = 8.175 ns; Loc. = LC_X14_Y8_N7; Fanout = 2; REG Node = 'lcd0:mylcd\|lcd_data\[1\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.980 ns" { clockdiv:div|clock_int lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.28 % ) " "Info: Total cell delay = 3.375 ns ( 41.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 58.72 % ) " "Info: Total interconnect delay = 4.800 ns ( 58.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|lcd_data[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.967 ns + Longest register pin " "Info: + Longest register to pin delay is 4.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd0:mylcd\|lcd_data\[1\] 1 REG LC_X14_Y8_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y8_N7; Fanout = 2; REG Node = 'lcd0:mylcd\|lcd_data\[1\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "lcd0.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcd0.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.645 ns) + CELL(2.322 ns) 4.967 ns data_out\[1\] 2 PIN PIN_114 0 " "Info: 2: + IC(2.645 ns) + CELL(2.322 ns) = 4.967 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'data_out\[1\]'" {  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.967 ns" { lcd0:mylcd|lcd_data[1] data_out[1] } "NODE_NAME" } } { "lcdcont.vhd" "" { Text "E:/old project/CPLD2.3/EPM Debug OK edition/lcd_palace/lcdcont.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.75 % ) " "Info: Total cell delay = 2.322 ns ( 46.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.645 ns ( 53.25 % ) " "Info: Total interconnect delay = 2.645 ns ( 53.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.967 ns" { lcd0:mylcd|lcd_data[1] data_out[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.967 ns" { lcd0:mylcd|lcd_data[1] {} data_out[1] {} } { 0.000ns 2.645ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.175 ns" { clk clockdiv:div|clock_int lcd0:mylcd|lcd_data[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.175 ns" { clk {} clk~combout {} clockdiv:div|clock_int {} lcd0:mylcd|lcd_data[1] {} } { 0.000ns 0.000ns 1.738ns 3.062ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.967 ns" { lcd0:mylcd|lcd_data[1] data_out[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.967 ns" { lcd0:mylcd|lcd_data[1] {} data_out[1] {} } { 0.000ns 2.645ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}