mux_lac.tdf

运用Quartus在LCM中显示静态宫殿图形

--lpm_mux CASCADE_CHAIN=IGNORE DEVICE_FAMILY=Cyclone IGNORE_CASCADE_BUFFERS=OFF LPM_SIZE=16 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
--VERSION_BEGIN 4.0 cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 10 
SUBDESIGN mux_lac
( 
	data[15..0]	:	input;
	result[0..0]	:	output;
	sel[3..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[3..0]	: WIRE;
	sel_node[3..0]	: WIRE;
	w_data64w[3..0]	: WIRE;
	w_data65w[3..0]	: WIRE;
	w_data66w[3..0]	: WIRE;
	w_data67w[3..0]	: WIRE;
	w_data9w[15..0]	: WIRE;
	w_result10w	: WIRE;
	w_result111w	: WIRE;
	w_result112w	: WIRE;
	w_result128w	: WIRE;
	w_result129w	: WIRE;
	w_result145w	: WIRE;
	w_result59w	: WIRE;
	w_result60w	: WIRE;
	w_result61w	: WIRE;
	w_result62w	: WIRE;
	w_result63w	: WIRE;
	w_result73w	: WIRE;
	w_result74w	: WIRE;
	w_result94w	: WIRE;
	w_result95w	: WIRE;
	w_sel68w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result10w);
	sel_ffs_wire[] = ( sel[3..0]);
	sel_node[] = ( sel_ffs_wire[3..2], sel[1..0]);
	w_data64w[3..0] = w_data9w[3..0];
	w_data65w[3..0] = w_data9w[7..4];
	w_data66w[3..0] = w_data9w[11..8];
	w_data67w[3..0] = w_data9w[15..12];
	w_data9w[] = ( data[15..0]);
	w_result10w = w_result59w;
	w_result111w = (((w_data66w[1..1] & w_sel68w[0..0]) & (! w_result112w)) # (w_result112w & (w_data66w[3..3] # (! w_sel68w[0..0]))));
	w_result112w = (((w_data66w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data66w[2..2])));
	w_result128w = (((w_data67w[1..1] & w_sel68w[0..0]) & (! w_result129w)) # (w_result129w & (w_data67w[3..3] # (! w_sel68w[0..0]))));
	w_result129w = (((w_data67w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data67w[2..2])));
	w_result145w = (((w_result60w & (! sel_node[3..3])) & (! sel_node[2..2])) # (sel_node[3..3] & (sel_node[2..2] # w_result62w)));
	w_result59w = (((w_result61w & sel_node[2..2]) & (! w_result145w)) # (w_result145w & (w_result63w # (! sel_node[2..2]))));
	w_result60w = w_result73w;
	w_result61w = w_result94w;
	w_result62w = w_result111w;
	w_result63w = w_result128w;
	w_result73w = (((w_data64w[1..1] & w_sel68w[0..0]) & (! w_result74w)) # (w_result74w & (w_data64w[3..3] # (! w_sel68w[0..0]))));
	w_result74w = (((w_data64w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data64w[2..2])));
	w_result94w = (((w_data65w[1..1] & w_sel68w[0..0]) & (! w_result95w)) # (w_result95w & (w_data65w[3..3] # (! w_sel68w[0..0]))));
	w_result95w = (((w_data65w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data65w[2..2])));
	w_sel68w[1..0] = sel_node[1..0];
END;
--VALID FILE