adcint.vhd

来自「通过ADC0809对模拟信号进行采样」· VHDL 代码 · 共 47 行

library ieee;
use ieee.std_logic_1164.all;
entity adcint is
port(d:in std_logic_vector(7 downto 0);
    clk,eoc:in std_logic;
    ale,start,oe,adda,lock0:out std_logic;
     q:out std_logic_vector(7 downto 0)
     );
end adcint;
architecture behav of adcint is
type states is (st0,st1,st2,st3,st4);
signal current_state,next_state:states:=st0;
signal regl:std_logic_vector(7 downto 0);
signal lock:std_logic;
begin 
adda<='1';
q<=regl;
lock0<=lock;
com:process(current_state,eoc)
begin
case current_state is 
when st0=>ale<='0';start<='0';lock<='0';oe<='0';
next_state<=st1;
when st1=>ale<='1';start<='1';lock<='0';oe<='0';
next_state<=st2;
when st2=>ale<='0';start<='0';lock<='0';oe<='0';
if(eoc='1')then next_state<=st3;
else next_state<=st2;
end if;
when st3=>ale<='0';start<='0';lock<='0';oe<='1';
next_state<=st4;
when st4=>ale<='0';start<='0';lock<='1';oe<='1';
next_state<=st0;
when others=>next_state<=st0;
end case;
end process com;
reg:process(clk)
begin
if(clk'event and clk='1') then current_state<=next_state;
end if;
end process reg;
latch1:process(lock)
begin
if lock='1' and lock'event then regl<=d;
end if;
end process latch1;
end behav;