shujucaiji.fit.qmsg

通过ADC0809对模拟信号进行采样

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock in PIN 17 " "Info: Automatically promoted some destinations of signal \"clk\" to use Global clock in PIN 17" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt10b:inst1\|clkout~7 " "Info: Destination \"cnt10b:inst1\|clkout~7\" may be non-global or may not use global clock" {  } { { "cnt10b.vhd" "" { Text "D:/shujucaiji/cnt10b.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 144 48 216 160 "clk" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt10b:inst1\|clkout~7 Global clock " "Info: Automatically promoted some destinations of signal \"cnt10b:inst1\|clkout~7\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "inclock " "Info: Destination \"inclock\" may be non-global or may not use global clock" {  } { { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 336 776 952 352 "inclock" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "cnt10b.vhd" "" { Text "D:/shujucaiji/cnt10b.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "adcint:inst\|current_state.st4 Global clock " "Info: Automatically promoted some destinations of signal \"adcint:inst\|current_state.st4\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lock0 " "Info: Destination \"lock0\" may be non-global or may not use global clock" {  } { { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 184 776 952 200 "lock0" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "adcint:inst\|oe " "Info: Destination \"adcint:inst\|oe\" may be non-global or may not use global clock" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 6 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt10b:inst1\|clkout~7 " "Info: Destination \"cnt10b:inst1\|clkout~7\" may be non-global or may not use global clock" {  } { { "cnt10b.vhd" "" { Text "D:/shujucaiji/cnt10b.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "adcint:inst\|current_state.st0 " "Info: Destination \"adcint:inst\|current_state.st0\" may be non-global or may not use global clock" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clr Global clock in PIN 16 " "Info: Automatically promoted signal \"clr\" to use Global clock in PIN 16" {  } { { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 336 48 216 352 "clr" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}